MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 204
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MPC8313CZQADDC
Manufacturer Part Number
MPC8313CZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313CZQADDC
Processor Series
MPC8313
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8313CZQADDC
Manufacturer:
Freescale Semiconductor
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10 000
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1
Address 0x0_0A00
Reset
Reset, Clocking, and Initialization
Table 4-34
4-38
Reset
16–31
See
9–15
Bits
2–3
4–7
0
1
8
W
W
R LBCM DDRCM
R
1
Table 4-34
16
COREPLL
n
n
0
DDRCM
Name
LBCM
SPMF
CKID
defines the system PLL mode register bit fields.
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
for reset values.
n
n
1
DDR SDRAM memory controller clock mode.
Reserved, should be cleared.
System PLL multiplication factor
SYS_CLK_IN division factor. Reflects the value of
CFG_CLKIN_DIV input signal during the reset flow.
Reserved, should be cleared.
Local bus memory controller clock mode.
Core PLL configuration.
n
n
2
—
Table 4-34. System PLL Mode Register Bit Settings
n
n
3
Figure 4-13. System PLL Mode Register
n
n
4
Meaning
n
n
SPMF
n
n
n
n
7
—
CKID
n
n
8
Section 4.3.2.1, “Reset Configuration Word Low
Register (RCWLR)”
Section 4.3.2.1, “Reset Configuration Word Low
Register (RCWLR)”
Section 4.3.2.1.1, “System PLL Configuration”
Section 4.3.1.2, “SYS_CLK_IN Division”
See the hardware specifications for this device
—
n
n
9
n
n
n
n
Description
COREPLL
—
Freescale Semiconductor
n
n
Access: Read only
n
n
n
n
15
31
n
n
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