MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1200

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

D–D
Coherent system bus (CSB)
Completion unit, overview, 7-8
Condition register (CR), 7-16
Configuration
Controller registers, 14-67
Core interface
Core, see e300 core
CR (condition register)
Critical input (cint) interrupt, 7-33
Critical interrupt
Crypto-channel
Crypto-channel registers, 14-55
CSB arbiter and bus monitor
Index-2
subsystem block diagram, 4-29
system
arbiter, see also CSB arbiter and bus monitor
overview, 6-1
boot sequencer, 4-17
DDR, 9-9–9-29, 9-31
eTSEC interfaces, 15-192
LBC
PCI
reset, 4-9
overview, 7-16
exception enable (G2_LE only), 7-18
configuration register, 14-55
coherent system bus, 6-1
error handling sequence, 6-16
features, 6-1
functionality
PCI_SYNC_IN, 4-4
PCI_SYNC_OUT, 4-4
SYS_CLK_IN, 4-3
USB_CLK_IN, 4-3
domains, 4-30
registers
configuration register (LBCR), 10-31
host/agent mode, 13-3
PCI arbiter, 13-4
sampled signals, 3-12
see also Reset, configuration
arbitration policy, 6-10
bus error detection, 6-13
configuration, 4-37–4-41
address bus arbitration after ARTRY, 6-13
address bus arbitration with PRIORITY[0:1], 6-11
address bus arbitration with REPEAT, 6-12
address bus parking, 6-13
data bus arbitration, 6-13
address only transaction type, 6-14
address time out, 6-13
data time out, 6-14
MPC8313E PowerQUICC™ II Pro Integrated Processor Reference Manual, Rev. 2
D
Data address translation, 7-18
Data cache enable, 7-22
Data cache flash invalidate, 7-22
Data cache lock, 7-22
Data cache way lock, 7-25
Data encryption standard execution units (DEU), 14-19,
Data TLB miss on load interrupt, 7-33
Data TLB miss on store interrupt, 7-33
DBAT, see Block address translation (BAT)
DDR controller
initialization sequence, 6-16
memory map/register definition, 6-2
overview, 6-1
registers, 6-2–6-10
address signal mappings, 9-4
block diagram, 9-2, 9-29
clock distribution, 9-42
configuration, example, 9-31
data beat ordering, 9-48
features, 9-2
functional description, 9-29
initialization/application information, 9-49
memory map/register definition, 9-8
modes of operation, 9-3
on-die termination for CSs, 9-7
page mode and logical bank retention, 9-48
register descriptions, 9-9
SDRAM operation, 9-32
self-refresh
signals summary, 9-3
14-40
programming different memory types, 9-50
by acronym, see Register Index
configuration registers, 9-9–9-29
address multiplexing, 9-34
initialization sequence, 9-53
JEDEC standard interface commands, 9-37
mode-set command timing, 9-42
organizations supported, 9-33
refresh operation, 9-44
registered DIMM mode, 9-43
timing, 9-39
write timing adjustments, 9-43
operation in sleep mode, 9-47
see also Signals, DDR
illegal (ECIWX/ECOWX) transaction type, 6-15
reserved transaction type, 6-15
transfer error, 6-14
power-saving modes, 9-45
timing, 9-45
Freescale Semiconductor
Index