MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1088

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

I
17.3
Table 17-3
17-4
2
C Interfaces
Signal
SCL1,
SDA1,
0x0_301C–
SCL2
SDA2
0x0_300C
0x0_30FF
0x0_310C
0x0_3000
0x0_3004
0x0_3008
0x0_3010
0x0_3014
0x0_3100
0x0_3104
0x0_3108
0x0_3110
Address
Memory Map/Register Definition
lists the I
I/O
I/O Serial clock. Performs as an input when the device is programmed as an I
I/O Serial data. Performs as an input when the device is in a receiving mode. SDA n also performs as an output
O
O
I
I
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
an output when the device is programmed as an I
As outputs for the bidirectional serial clock, these signals operate as described below.
As inputs for the bi-directional serial clock, these signals operate as described below.
signal when the device is transmitting (as an I
As outputs for the bi-directional serial data, these signals operate as described below.
As inputs for the bi-directional serial data, these signals operate as described below.
I2C1ADR—I
I2C1FDR—I
I2C1CR—I
I2C1SR—I
I2C1DR—I
I2C1DFSRR—I
Reserved, should be cleared
I2C2ADR—I
I2C2FDR—I
I2C2CR—I
I2C2SR—I
I2C2DR—I
Meaning
Meaning
Meaning
Meaning
State
State
State
State
2
C–specific registers and their addresses.
Table 17-2. I
Asserted/Negated—Driven along with SDA n as the clock for the data.
Asserted/Negated—The I
Asserted/Negated—Data is driven.
Asserted/Negated—Used to receive data from other devices. The bus is assumed to be busy when
2
2
2
2
2
2
C1 status register
C2 status register
C1 control register
C1 data register
C2 control register
C2 data register
2
2
2
2
C1 frequency divider register
C2 frequency divider register
C1 address register
C2 address register
2
is assumed to be busy when this signal is detected low.
SDA n is detected low.
C1 digital filter sampling rate register
2
C Interface Signals—Detailed Signal Descriptions
I
2
C Register
Table 17-3. I
2
C unit uses this signal to synchronize incoming data on SDA n . The bus
2
C Memory Map
2
C master or a slave).
Description
2
C master.
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
2
C slave. SCL n also performs as
Reset
0x00
0x00
0x00
0x81
0x00
0x10
0x00
0x00
0x00
0x81
0x00
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Freescale Semiconductor
Section/Page
17.3.1.1/17-5
17.3.1.2/17-6
17.3.1.3/17-7
17.3.1.4/17-8
17.3.1.5/17-9
17.3.1.6/17-9
17.3.1.1/17-5
17.3.1.2/17-6
17.3.1.3/17-7
17.3.1.4/17-8
17.3.1.5/17-9
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