MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 627

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

the low priority group, it can be seen that each high priority initiator is guaranteed at least 1 out of 3
transaction slots, and each low priority initiator is guaranteed at least 1 out of 6 slots. Assuming all devices
are requesting the bus, the grant sequence (with device 1 being the current master) is as follows: 0, 2, the
PCI controller, 0, 2, 1, 0, 2, the PCI controller, and so on. If, for example, device 2 is not requesting the
bus, the grant sequence becomes 0, the PCI controller, 0, 1, 0, the PCI controller, and so on. If device 2
now requests the bus at a point in the sequence when device 0 is conducting a transaction and the PCI
controller is the next grant, then the PCI controller’s grant is removed, and the higher-priority device 2 is
awarded the next grant.
13.4.1.3
The broken master feature allows the arbiter to lock out any masters that are broken or ill-behaved. This
feature is controlled by programming the PCI arbiter control register. When the broken master feature is
enabled, a granted device that does not assert PCI_FRAME within 16 PCI clock cycles after the bus is idle,
has its grant removed and subsequent requests are ignored until its REQ is negated for at least one clock
cycle. This prevents ill-behaved masters from monopolizing the bus. When the broken master feature is
disabled, a device that requests the bus and receives a grant never loses its grant until and unless it begins
a transaction or negates its REQ signal. Note that disabling the broken master feature is not recommended.
13.4.1.4
The PCI controller implements the master latency timer register (see
Configuration
expires, the PCI controller checks the state of its PCI_GNT signals. If the PCI_GNT signal is not asserted,
the PCI controller completes one more data phase and relinquishes the bus. The master latency timer can
be disabled if needed (see
information).
Freescale Semiconductor
e
Broken Master Lock-Out
Master Latency Timer
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Register”) to prevent itself from monopolizing the bus. When the master latency timer
(1/3)
0
High-Priority Group
Section 13.3.3.24, “PCI Function Configuration Register,”
(1/3)
2
Figure 13-47. PCI Arbitration Example
(1/3)
Low
Low-Priority Group
Section 13.3.3.10, “Latency Timer
Bridge
(1/6)
(1/6)
PCI
1
for more
PCI Bus Interface
13-45