MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1002
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MPC8313CZQADDC
Manufacturer Part Number
MPC8313CZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313CZQADDC
Processor Series
MPC8313
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Universal Serial Bus Interface
H-Frame boundaries for the host controller correspond to increments of FRINDEX[13–3]. Micro-frame
numbers for the H-Frame are tracked by FRINDEX[2–0]. B-Frame boundaries are visible on the
high-speed bus via changes in the SOF token's frame number. Micro-frame numbers on the high-speed bus
are only derived from the SOF token's frame number (that is, the high-speed bus will see eight SOFs with
the same frame number value). H-Frames and B-Frames have the fixed relationship (that is, B-Frames lag
H-Frames by one micro-frame time) illustrated in
naturally aligned to H-Frames. Software schedules transactions for full- and low-speed periodic endpoints
relative the H-Frames. The result is these transactions execute on the high-speed bus at exactly the right
time for the USB 2.0 hub periodic pipeline. As described in
(FRINDEX),”
which lags the FRINDEX register bits [13–3] by one micro-frame count.
required relationship between the value of FRINDEX and the value of SOFV. This lag behavior can be
accomplished by incrementing FRINDEX[13–3] based on carry-out on the 7 to 0 increment of
FRINDEX[2–0] and incrementing SOFV based on the transition of 0 to 1 of FRINDEX[2–0].
Software is allowed to write to FRINDEX.
provides the requirements that software should adhere when writing a new value in FRINDEX.
16-74
Micro-Frames
HC Periodic
Figure 16-46. Relationship of Periodic Schedule Frame Boundaries to Bus Frame Boundaries
Schedule
HS Bus
Frames
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
the SOF Value can be implemented as a shadow register (in this example, called SOFV),
7
0
SS
HC Periodic Schedule
Frame Boundaries
1
Full/Low-Speed
Interface Data Structure
Transaction
2
CS
H-Frame N
3
CS
B-Frame N
4
CS
5
CS
Section 16.3.2.4, “Frame Index Register (FRINDEX),”
6
Figure
7
0
SS
16-46. The host controller's periodic schedule is
Section 16.3.2.4, “Frame Index Register
1
Full/Low-Speed
Interface Data Structure
Transaction
HS/FS/LS Bus
Frame Boundaries
2
CS
H-Frame N+1
3
CS
B-Frame N+1
Table 16-65
4
CS
5
CS
6
Freescale Semiconductor
illustrates the
7
0
1
2
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