MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1080

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
16.9.1.5.5
The maximum number of embedded transaction translators that is currently supported is one as indicated
by the N_TT field in the HCSPARAMS register. See
Parameters (HCSPARAMS),”
16.9.2
The co-existence of a device operational controller within the DR module has little effect on EHCI
compatibility for host operation except as noted in this section.
16.9.3
Some of the reserved fields and reserved addresses in the capability registers and operational registers have
use in device mode, the following must be adhered to:
16.9.4
The SOF interrupt is a free running 125 µsec interrupt for host mode. EHCI does not specify this interrupt,
but it has been added for convenience and as a potential software time base. Note that the free running
interrupt is shared with the device-mode start-of-frame interrupt. See
Register (USBSTS),”
information.
16-152
•
•
— Abort of pending start-splits
— Abort of pending complete-splits
Write operations to all EHCI reserved fields (some of which are device fields in the DR module)
in the operation registers should always be written to zero. This is an EHCI requirement of the
device controller driver that must be adhered to.
Read operations by the module must properly mask EHCI reserved fields (some of which are
device fields in the DR module registers).
– EOF (and not started in microframes 6)
– Idle for more than 4 microframes
– EOF
– Idle for more than 4 microframes
Device Operation
Non-Zero Fields the Register File
SOF Interrupt
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
There is no data schedule mechanism for these transactions other than the
microframe pipeline. The embedded TT assumes the number of packets
scheduled in a frame does not exceed the frame duration (1 msec) or else
undefined behavior may result.
Multiple Transaction Translators
and
Section 16.3.2.3, “USB Interrupt Enable Register (USBINTR),”
for more information.
NOTE
Section 16.3.1.3, “Host Controller Structural
Section 16.3.2.2, “USB Status
Freescale Semiconductor
for more