MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 923

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
This advertises to the Link Partner that the TBI supports PAUSE and Full Duplex mode and does not support Half Duplex mode
Set up the MII Mgmt for a write cycle to TBI’s AN Advertisement register (write the PHY address and Register address),
Set source clock divide by 14, for example, to insure that TSEC_MDC clock speed is not greater than 2.5 MHz.
Set up the MII Mgmt for a read cycle to TBI’s Control register (write the TBI’s address and Register address),
The AN Advertisement register is at offset address 0x04 from the TBI’s address. (in this case 0x10)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Write to MII Mgmt Control with 16-bit data intended for TBI’s AN Advertisement register,
Perform an MII Mgmt read cycle to verify state of TBI Control Register(0ptional)
(Uses the TBI address and Register address placed in MIIMADD register),
read the MIIMSTAT and look for AN Enable and other bit information.
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
Table 15-176. RTBI Mode Register Initialization Steps
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]
The control register (CR) is at offset address 0x0 from TBIPA.
MIIMCON[0000_0000_0000_0000_0000_0001_1010_0000]
MIIMCFG[0000_0000_0000_0000_0000_0000_0000_0101]
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0000]
MIIMADD[0000_0000_0000_0000_0001_0000_0000_0100]
ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
TBIPA[0000_0000_0000_0000_0000_0000_0001_0000]
This indicates that the eTSEC MII Mgmt bus is idle.
This indicates that the write cycle was completed.
Check to see if MII Mgmt write is complete.
(This example has Statistics Enable = 1)
Perform an MII Mgmt write cycle to TBI.
Assign a Physical address to the TBI,
Setup the MII Mgmt clock speed,
to 02608C:876543, for example.
to 02608C:876543, for example.
Initialize MAC Station Address,
Initialize MAC Station Address,
(I/F Mode = 2, Full Duplex = 1)
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
When MIIMIND[BUSY]=0,
set to 16, for example.
Initialize MACCFG2,
Initialize ECNTRL,
Clear Soft_Reset,
Set Soft_Reset,
Enhanced Three-Speed Ethernet Controllers
15-205