MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 957

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Freescale Semiconductor
Bits
8
7
6
Name
SUSP Suspend.
FPR
PR
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Port reset.
Host mode:
Device mode:
1 Port is in reset.
0 Port is not in reset.
This field is zero if Port Power(PP) is zero.
Host mode:
0x Disable
10 Enable
11 Suspend
Device mode:
1 Port in suspend state.
0 Port not in suspend state. Default.
In device mode this bit is a read-only status bit.
Force port resume. This bit is not-EHCI compatible.
1 Resume detected/driven on port.
0 No resume (K-state) detected/driven on port.
Host mode:
Device mode:
• When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision
• This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register.
• The port enabled bit (PE) and suspend (SUSP) bit define the port states as follows:
• When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The
• The module unconditionally sets this bit to zero when software clears the FPR bit. A write of zero to this bit
• This field is zero if Port Power (PP) is zero in host mode.
• Software sets this bit to one to drive resume signaling. The controller sets this bit to one if a J-to-K transition
• Note that when the controller owns the port, the resume sequence follows the defined sequence
• This field is zero if Port Power (PP) is zero in host mode.
• After the device has been in Suspend State for 5 msec or more, software must set this bit to one to drive
2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior
is different from EHCI where the host controller driver is required to set this bit to a zero after the reset
duration is timed in the driver.
blocking occurs at the end of the current transaction if a transaction was in progress when this bit was
written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not
change until the port is suspended and that there may be a delay in suspending a port if there is a
transaction currently in progress on the USB.
is ignored by the host controller. If host software sets this bit to a one when the port is not enabled (that is,
port enabled bit is a zero) the results are undefined.
is detected while the port is in the Suspend state. When this bit transitions to a one a J-to-K transition is
detected, USBSTS[PCI] (port change detect) is also set. This bit will automatically change to zero after the
resume sequence is complete. This behavior is different from EHCI where the host controller driver is
required to set this bit to a zero after the resume duration is timed in the driver.
documented in the USB Specification Revision 2.0. The resume signaling (Full-speed ‘K’) is driven on the
port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed
idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the
port control state switches to HS or FS idle.
resume signaling before clearing. The USB DR controller will set this bit to one if a J-to-K transition is
detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal
operation. Also, when this bit transitions to a one because a J-to-K transition detected, USBSTS[PCI] is also
set.
Table 16-23. PORTSC Register Field Descriptions (continued)
Description
Universal Serial Bus Interface
16-29