MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 163

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

3.2
The signals that serve alternate functions as configuration input signals during system reset are
summarized in
Chapter 4, “Reset, Clocking, and Initialization.”
3.3
When a system reset is recognized (PORESET or HRESET are asserted), the device aborts all current
internal and external transactions and releases all bidirectional I/O signals to a high-impedance state. See
Chapter 4, “Reset, Clocking, and Initialization,”
During reset, the device ignores most input signals (except for the reset configuration signals) and drives
most of the output-only signals to an inactive state.
Freescale Semiconductor
3
4
The LB_POR_CFG_BOOT_ECC_DIS function will be selected on the TSEC_MDC pin whenever HRESET is
asserted; the pin will act as TSEC_MDC at all other times. The reset block will sample this signal on PORESET
negation only; the sampled value is then passed to the eLBC controller to enable/disable ECC checking during boot
time. An internal pull-down resistor has been added to this pad to enable the boot-time ECC checking by default. A
pull-up resistor, via a three-state buffer, is needed during HRESET assertion period to disable ECC checking during
boot time.
Must be connected to a 10K ±1% precision resistor if using the integrated USB PHY through the UTMI.
Configuration Signals Sampled at Reset
Output Signal States During Reset
MODT[0:1]
MDM[0:3]
Interface
MCS[0:1]
MBA[0:2]
MA[0:14]
MRAS
MCAS
MCKE
MWE
MCK
MCK
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table
Dedicated pin
Dedicated pin
3-3. The detailed interpretation of their voltage levels during reset is described in
Functional
Interface
eTSEC2
Table 3-4. Output Signal States During System Reset
DDR data mask
DDR bank select
DDR address
DDR write enable
DDR row address strobe
DDR column address strobe
DDR chip select (2/DIMM)
DDR clock enable
DDR differential clocks
DDR differential clocks
DRAM on-die termination
Table 3-3. Reset Configuration Signals
Functional Signal Name
None (dedicated pin)
None (dedicated pin)
TSEC2_TXD[3:0]
Signal
for a complete description of the reset functionality.
Table 3-4
CFG_RESET_SOURCE[0:3]
Reset Configuration Name
shows the states of the output-only signals.
CFG_LBIU_MUX_EN
CFG_CLKIN_DIV
State During Reset
Both ‘Z’
Both ‘0’
All ‘Z’
All ‘Z’
All ‘Z’
‘Z’
‘Z’
‘0’
‘0’
‘1’
‘Z
Signal Descriptions
3-29