MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 543

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

conclusion of the sequence, eLBC will issue a command complete interrupt (LTESR[CC]) if interrupts are
enabled. MDR[AS3–AS0] then can be read to obtain the first 4 bytes of NAND Flash ID.
10.5.4.4
An example of configuring FCM to execute a random page read command to large-page NAND Flash is
shown in
buffer RAM, checking ECC as it proceeds. The sequence is initiated by writing FMR[OP] = 10, and
issuing a special operation to the bank. A few cycles before completion itself, FECCn gets updated with
the ECC bytes for the main region validated by FECCn[0]. At the conclusion of the sequence, eLBC will
issue a command complete interrupt (LTESR[CC]) if interrupts are enabled. Once the sequence has
completed, the shared buffer (buffer 1 for page index 5) and transfer error registers (LTECCR that reports
the 512 blocks with unibit /multibit errors if any) are valid.
Freescale Semiconductor
Table
Register
FBCR
FBAR
FPAR
Register
MDR
FCR
FIR
FBCR
FBAR
FPAR
MDR
FCR
NAND Flash Page Read Command Sequence Example
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
FIR
10-47. This sequence reads an entire page (main and spare region) into the shared FCM
Table 10-47. FCM Register Settings for Page Read (OR n [PGS] = 1)
(e.g. block 0x00010ab4)
locates page 5, buffer 1)
Table 10-46. FCM Register Settings for ID Read (OR n [PGS] = 1)
(e.g. 0x00005000
Initial Contents
Initial Contents
0x4125E000
0x00300000
0x00000000
0x43BBBBB0
block index
page offset
0x90000000
0x00000000
—
—
—
—
CMD0 = 0x00 = random read address entry;
CMD1 = 0x30 = read page
BLK locates index of 128-Kbyte block
PI locates page index in BLK;
PI mod 2 indexes FCM buffer RAM;
MS = 0 and CI = 0
BC = 0 to read entire 2112-byte page with ECC check
unused
OP0 = CM0 = command 0;
OP1 = CA = column address;
OP2 = PA = page address;
OP3 = CM1 = command 1;
OP4 = RBW = wait on Flash ready and read data into FCM buffer;
OP5–OP7 = NOP
CMD0 = 0x90 = read ID command; other commands unused
unused
unused
unused
AS0 = 0x00 = dummy address for read ID command;
AS0–AS3 return with first 4 bytes of ID code
OP0 = CM0 = command 0;
OP1 = UA = user address from MDR;
OP2–OP6 = RS = read 4 bytes ID into MDR[AS3–AS0];
OP7 = NOP
Description
Description
Enhanced Local Bus Controller
10-95