MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 639

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

13.4.5
This section describes PCI bus errors.
13.4.5.1
During valid 32-bit address and data transfers, parity covers all 32 address/data lines and the 4
command/byte enable lines regardless of whether or not all lines carry meaningful information. Byte lanes
not actually transferring data are driven with stable (albeit meaningless) data and are included in the parity
calculation. During configuration, special cycle or interrupt acknowledge commands, some address lines
are not defined but are still driven to stable values and included in the parity calculation.
Even parity is calculated for all PCI operations: the value of PCI_PAR is generated such that the number
of ones on PCI_AD[31:0], PCI_C/BE[3:0] and PCI_PAR equals an even number. The PCI_PAR signal is
driven when the address/data lines are driven and follow the corresponding address or data by one clock.
The PCI controller checks the parity after all valid address phases (the assertion of PCI_FRAME) and for
valid data transfers (PCI_IRDY and PCI_TRDY asserted) involving the PCI controller. When an address
or data parity error is detected, the detected-parity-error bit in the configuration space status register is set
(see
13.4.5.2
Except for setting the detected-parity-error bit, all parity error reporting and response is controlled by the
parity-error-response bit (see
information). If the parity-error-response bit is cleared, the PCI controller completes all transactions
regardless of parity errors (address or data). If the bit is set, the PCI controller asserts PCI_PERR two
clocks after the actual data transfer in which a data parity error is detected, and keeps PCI_PERR asserted
for one clock. When acting as an initiator during a read transaction or as a target involved in a write to
system memory the PCI controller asserts PCI_PERR.
Freescale Semiconductor
Section 13.3.3.4, “PCI Status Configuration
Error Functions
Parity
Error Reporting
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Section 13.3.3.3, “PCI Command Configuration Register,”
Register.”)
for more
PCI Bus Interface
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