MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 53

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

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Freescale Semiconductor
Frame Span Traversal Node Structure ................................................................................ 16-66
Derivation of Pointer into Frame List Array....................................................................... 16-72
General Format of Asynchronous Schedule List ................................................................ 16-72
Frame Boundary Relationship Between HS Bus and FS/LS Bus ....................................... 16-73
Relationship of Periodic Schedule Frame Boundaries to Bus Frame Boundaries .............. 16-74
Example Periodic Schedule ................................................................................................ 16-76
Example Association of iTDs to Client Request Buffer ..................................................... 16-79
Generic Queue Head Unlink Scenario ................................................................................ 16-84
Asynchronous Schedule List with Annotation to Mark Head of List................................. 16-85
Example Mapping of qTD Buffer Pointers to Buffer Pages ............................................... 16-87
Host Controller Asynchronous Schedule Split-Transaction State Machine ....................... 16-90
Split Transaction, Interrupt Scheduling Boundary Conditions ........................................... 16-93
General Structure of EHCI Periodic Schedule Utilizing Interrupt Spreading .................... 16-94
Example Host Controller Traversal of Recovery Path via FSTNs...................................... 16-96
Split Transaction State Machine for Interrupt..................................................................... 16-99
Split Transaction, Isochronous Scheduling Boundary Conditions ................................... 16-105
siTD Scheduling Boundary Examples .............................................................................. 16-107
Split Transaction State Machine for Isochronous ............................................................. 16-110
Endpoint Queue Head Organization ................................................................................. 16-123
Endpoint Queue Head Layout........................................................................................... 16-124
Endpoint Transfer Descriptor (dTD)................................................................................. 16-126
USB 2.0 Device States ...................................................................................................... 16-130
Endpoint Queue Head Diagram ........................................................................................ 16-142
Software Link Pointers...................................................................................................... 16-144
ULPI Timing ..................................................................................................................... 16-154
Sending of RX CMD......................................................................................................... 16-155
ULPI Data Transmit (NOPID) .......................................................................................... 16-155
ULPI Data Transmit (PID)................................................................................................ 16-155
ULPI Data Receive ........................................................................................................... 16-156
ULPI Register Write.......................................................................................................... 16-156
ULPI Register Read .......................................................................................................... 16-156
I
I
I
I
I
I
I
I
EEPROM Contents ............................................................................................................. 17-17
EEPROM Data Format for One Register Preload Command............................................. 17-18
2
2
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2
2
C Block Diagram................................................................................................................ 17-1
Cn Address Register (I2CnADR)....................................................................................... 17-5
Cn Frequency Divider Register (I2CnFDR) ...................................................................... 17-6
Cn Control Register (I2CnCR)........................................................................................... 17-7
Cn Status Register (I2CnSR) ............................................................................................. 17-8
Cn Data Register (I2CnDR) ............................................................................................... 17-9
Cn Digital Filter Sampling Rate Register (I2CnDFSRR) .................................................. 17-9
C Interface Transaction Protocol...................................................................................... 17-10
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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