MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 427

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

be constructed using x8, x16, or x32 memory devices. The memory technologies supported are 64 Mbits,
128 Mbits, 256 Mbits, 512 Mbits, 1 Gbit, 2 Gbits, and 4 Gbits. Four data qualifier (DQM) signals provide
byte selection for memory accesses.
Table 9-24
MDQS[0:3], and MDQ[0:31] when DDR SDRAM memories are used with x8 or x16 devices.
9.5.1.1
Although the DDR memory controller multiplexes row and column address bits onto 15 memory address
signals and 3 logical bank select signals, a physical bank may be implemented with memory devices
requiring fewer than 30 address bits. The physical bank may be configured to provide from 12 to 15 row
address bits, plus 2 or 3 logical bank-select bits and from 8–11 column address bits.
Table 9-25
controller.
Freescale Semiconductor
SDRAM Device
128 Mbits
128 Mbits
256 Mbits
256 Mbits
512 Mbits
512 Mbits
64 Mbits
64 Mbits
1 Gbits
and
shows the DDR memory controller’s relationships between data byte lane0–3, MDM[0:3],
Supported DDR SDRAM Organizations
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
An 8-bit DDR SDRAM device has a DQM signal and eight data signals
(DQ[0:7]). A 16-bit DDR SDRAM device has two DQM signals associated
with specific halves of the 16 data signals (DQ[0:7] and DQ[8:15]).
DDR SDRAM is limited to 29 total address bits.
Table 9-26
1
Data Byte Lane
Device Configuration
0 (MSB)
Table 9-25. Supported DDR1 SDRAM Device Configurations
1
2
3
16 Mbits x 16
32 Mbits x 16
128 Mbits x 8
4 Mbits x 16
16 Mbits x 8
8 Mbits x 16
32 Mbits x 8
64 Mbits x 8
8 Mbits x 8
describe DDR SDRAM device configurations supported by the DDR memory
Table 9-24. Byte Lane to Data Relationship
Data Bus Mask
MDM[0]
MDM[1]
MDM[2]
MDM[3]
Row x Column x
Sub-bank Bits
12 x 10 x 2
13 x 10 x 2
13 x 11 x 2
13 x 10 x 2
14 x 11 x 2
12 x 9 x 2
12 x 8 x 2
12 x 9 x 2
13 x 9 x 2
NOTE
NOTE
Data Bus Strobe
MDQS[0]
MDQS[1]
MDQS[2]
MDQS[3]
32-Bit Bank Size
128 Mbytes
256 Mbytes
128 Mbytes
512 Mbytes
32 Mbytes
16 Mbytes
64 Mbytes
32 Mbytes
64 Mbytes
MDQ[16:23]
MDQ[24:31]
MDQ[8:15]
Data Bus
MDQ[0:7]
Two Banks of Memory
128 Mbytes
256 Mbytes
128 Mbytes
512 Mbytes
256 Mbytes
64 Mbytes
32 Mbytes
64 Mbytes
1 Gbyte
DDR Memory Controller
9-33