MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 407
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MPC8313CZQADDC
Manufacturer Part Number
MPC8313CZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313CZQADDC
Processor Series
MPC8313
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Table 9-9
Freescale Semiconductor
13–15
9–11
Bits
0–1
2–3
4–5
6–7
12
8
ACT_PD_EXIT Active powerdown exit timing (t
PRE_PD_EXIT Precharge powerdown exit timing (t
describes TIMING_CFG_0 fields.
Name
WWT
RWT
WRT
RRT
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
—
Read-to-write turnaround (t
turnaround. If 0 clocks is chosen, then the DDR controller uses a fixed number based on the CAS
latency and write latency. Choosing a value other than 0 adds extra cycles past this default
calculation. As a default the DDR controller determines the read-to-write turnaround as CL – WL +
BL/2 + 2. In this equation, CL is the CAS latency rounded up to the next integer, WL is the
programmed write latency, and BL is the burst length.
00 0 clocks
01 1 clock
Write-to-read turnaround. Specifies how many extra cycles are added between a write to read
turnaround. If 0 clocks is chosen, then the DDR controller uses a fixed number based on the, read
latency, and write latency. Choosing a value other than 0 adds extra cycles past this default
calculation. As a default, the DDR controller determines the write-to-read turnaround as WL – CL +
BL/2 + 1. In this equation, CL is the CAS latency rounded down to the next integer, WL is the
programmed write latency, and BL is the burst length.
00 0 clocks
01 1 clock
Read-to-read turnaround. Specifies how many extra cycles are added between reads to different
chip selects. As a default, 3 cycles are required between read commands to different chip selects.
Extra cycles may be added with this field. Note: If 8-beat bursts are enabled, then 5 cycles are the
default. Note that DDR2 does not support 8-beat bursts.
00 0 clocks
01 1 clock
Write-to-write turnaround. Specifies how many extra cycles are added between writes to different
chip selects. As a default, 2 cycles are required between write commands to different chip selects.
Extra cycles may be added with this field. Note: If 8-beat bursts are enabled, then 4 cycles are the
default. Note that DDR2 does not support 8-beat bursts.
00 0 clocks
01 1 clock
Reserved, should be cleared.
exiting active powerdown before issuing any command.
000
001
010
011
Reserved, should be cleared.
precharge powerdown before issuing any command.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
Reserved
1 clock
2 clocks
3 clocks
Table 9-9. TIMING_CFG_0 Field Descriptions
RTW
). Specifies how many extra cycles are added between a read to write
XARD
XP
and t
). Specifies how many clock cycles to wait after exiting
XARDS
Description
). Specifies how many clock cycles to wait after
10 2 clocks
11 3 clocks
10 2 clocks
11 3 clocks
10 2 clocks
11 3 clocks
10 2 clocks
11 3 clocks
100
101
110
111
4 clocks
5 clocks
6 clocks
7 clocks
DDR Memory Controller
9-13
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