MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1187

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

15.6.5.2, 15-170
15.6.6.2, 15-178
115.6.6.3, 15-182
15.7.1.5, 15-199
Chapter 16
16.1, 16-1
16.1, 16-2
16.2, 16-3
16.2.2, 16-4
16.3, 16-7
16.3.1.6, 16-11
16.3.2.13, 16.25
16.3.2.13, 16-27
16.3.2.27, 16-41
16.10, 16-155
17.3.1.2, 17-5
17.3.1.2, 17-7
17.3.1.3, 17-7
20.1, 20-1
20.2.1, 20-2
Freescale Semiconductor
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Modified Figure 15-145 and changed the name from ‘Alcatel MAC’ to ‘Ethernet
MAC.’
In Table 15-164, modified bit TR to clarify when truncation occurs on transmit.
In Table 15-165, corrected description of RxBD TR (truncation) field to state that
TR can also be set if a frame length equal to the maximum frame length is
received. Modified descriptions of bit LG.
In Table 15-178, changed SerDes and SGMII signal frequency from 625 MHz to
1250 MHz, TXD and RXD to TXDp/TXDn and RXDp/RXDn, respectively.
Throughout this chapter changed references from endpoint 5 to endpoint 2 and
removed offsets for endpoints 3, 4, and 5.
Changed ‘Access in Memory Map’ to match register figure; USBSTS, PORTSC,
OTGSC, ENDRPT Complete, and ENDPTCTRL. In figure, changed access to
‘Mixed from R/W,’ in memory map, changed reset values to match register
figures: USBCMD, FRIDEX, and PERIODICLISTBASE.
In Figure 16-1, updated diagram.
Table 16-1: removed mentioning of UTMI signals, as they are internal signals;
added UTMI PHY external signals.
Removed the note, ‘The ULPI signals are multiplexed with UTMI interface.’
Removed ENDPTCTRL3–5 registers.
In Figure 16-7, changed DEN reset value to 0011.
Corrected bit description by switching PORTSC[LS] bit 01 (J-state) with 10
(K-state). Also modified the order to 00,10,01,11.
In Table 16-22, for bits 11-10, modified the order of 00,01,10,11 to 00,10,01,11.
Changed PORTSC[PTX] to ‘Reserved.’
In Table 16-36, added the following note for bits 30 and 31: ‘PORTSC[PHCD] bit
must be set.’ Also for RefSel[1:0] changed bits 01 to 24 MHz instead of 16 MHz
and changed 00 to ‘Reserved’ instead of 12 MHz.
In Table 16-98, replaced all TBDs with actual values.
In Table 17-5, added the following notes:
1. The values shown in the table are applicable only for the default value of
DFSRR, refer to AN2919.
2. I
Replaced the clock ratio for controller clock : csb clock to 1:1.
In Table 17-6, replaced TSEC2CM with ENCCM and stated that I2C1 is
controllable through this, and clock ratios for I2C2 are not controllable and is
always 1:1 with CSB.
Removed the pull-up register for TCK.
In Table 20-1, removed reset values for all input signals.
2
C controller clock of I2C1 is derived from csb_clk/SCCR[SDHCCM].
Revision History
A-29