MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 1089

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

17.3.1
This section describes the I
value they return when read. That is, the register should be programmed by reading the value, modifying
appropriate fields, and writing back the value. The return value of the reserved fields should not be
assumed, even though the reserved fields return zero. This does not apply to the I
(I2CnDR).
17.3.1.1
Figure 17-2
when addressed as a slave. Note that this is not the address that is sent on the bus during the address-calling
cycle when the I
Table 17-4
Freescale Semiconductor
Bits
0–6
0x0_311C–
0x0_31FF
7
0x0_3114
Address
ADDR Slave address. Contains the specific slave address that is used by the I
Name
—
describes the bit settings of I2CnADR.
Register Descriptions
shows the I2CnADR register, which contains the address to which the I
Offset 0x0_3000
Reset
I
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2
C n Address Register (I2C n ADR)
I2C2DFSRR—I
Reserved, should be cleared
mode of the I
conditions that can cause I2C n SR[MIF] to be set, signaling an interrupt pending condition.
Reserved, should be cleared
W
R
2
C module is in master mode.
0
2
2
C interface is slave mode for an address match. Note that an address match is one of the
C registers in detail. Note that reserved bits should always be written with the
2
C2 digital filter sampling rate register
Figure 17-2. I
Table 17-3. I
Table 17-4. I2C n ADR Field Descriptions
I
2
C Register
2
C n Address Register (I2C n ADR)
2
C Memory Map (continued)
ADDR
All zeros
Description
Access
R/W
—
2
C interface. Note that the default
Access: Read/write
6
Reset
0x10
2
Cn data register
—
2
C interface responds
—
7
Section/Page
17.3.1.6/17-9
I
2
C Interfaces
—
17-5