MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 34

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Paragraph
Number
16.9.5.1
16.9.6
16.9.6.1
16.9.6.2
16.9.6.2.1
16.9.6.2.2
16.10
17.1
17.1.1
17.1.2
17.2
17.2.1
17.2.2
17.3
17.3.1
17.3.1.1
17.3.1.2
17.3.1.3
17.3.1.4
17.3.1.5
17.3.1.6
17.4
17.4.1
17.4.1.1
17.4.1.2
17.4.1.3
17.4.1.4
17.4.1.5
17.4.1.5.1
17.4.1.5.2
17.4.1.6
17.4.2
17.4.2.1
17.4.3
17.4.4
17.4.4.1
17.4.4.2
xxxiv
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Timing Diagrams ....................................................................................................... 16-154
Introduction.................................................................................................................... 17-1
External Signal Descriptions ......................................................................................... 17-3
Memory Map/Register Definition ................................................................................. 17-4
Functional Description................................................................................................. 17-10
Miscellaneous Variations from EHCI .................................................................... 16-153
Features...................................................................................................................... 17-2
Modes of Operation ................................................................................................... 17-2
Signal Overview ........................................................................................................ 17-3
Detailed Signal Descriptions ..................................................................................... 17-3
Register Descriptions................................................................................................. 17-5
Transaction Protocol ................................................................................................ 17-10
Arbitration Procedure .............................................................................................. 17-13
Handshaking ............................................................................................................ 17-14
Clock Control........................................................................................................... 17-14
Frame Adjust Register ....................................................................................... 16-153
Programmable Physical Interface Behavior ...................................................... 16-153
Discovery ........................................................................................................... 16-153
I
I
I
I
I
START Condition ................................................................................................ 17-11
Slave Address Transmission ................................................................................ 17-11
Repeated START Condition ................................................................................ 17-12
STOP Condition................................................................................................... 17-12
Protocol Implementation Details ......................................................................... 17-12
Address Compare—Implementation Details ....................................................... 17-13
Arbitration Control .............................................................................................. 17-14
Clock Synchronization......................................................................................... 17-15
Input Synchronization and Digital Filter ............................................................. 17-15
Digital Filter Sampling Rate Register (I2CnDFSRR) ........................................... 17-9
2
2
2
2
2
Cn Address Register (I2CnADR) ....................................................................... 17-5
Cn Frequency Divider Register (I2CnFDR)....................................................... 17-6
Cn Control Register (I2CnCR) ........................................................................... 17-7
Cn Status Register (I2CnSR) .............................................................................. 17-8
Cn Data Register (I2CnDR)................................................................................ 17-9
Port Reset....................................................................................................... 16-153
Port Speed Detection ..................................................................................... 16-154
Transaction Monitoring—Implementation Details.......................................... 17-12
Control Transfer—Implementation Details ..................................................... 17-12
Contents
I
2
Chapter 17
C Interfaces
Title
Freescale Semiconductor
Number
Page