MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 26

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

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15.5.3.6.42
15.5.3.6.43
15.5.3.6.44
15.5.3.6.45
15.5.3.6.46
15.5.3.6.47
15.5.3.6.48
15.5.3.7
15.5.3.7.1
15.5.3.7.2
15.5.3.8
15.5.3.8.1
15.5.3.9
15.5.3.9.1
15.5.3.9.2
15.5.3.10
15.5.3.10.1
15.5.3.10.2
15.5.3.10.3
15.5.3.10.4
15.5.3.10.5
15.5.3.10.6
15.5.3.10.7
15.5.3.10.8
15.5.3.10.9
15.5.3.10.10
15.5.3.10.11
15.5.3.10.12
15.5.3.10.13
15.5.3.10.14
15.5.4
15.5.4.1
15.5.4.1.1
15.5.4.1.2
15.5.4.1.3
15.5.4.2
15.5.4.2.1
15.5.4.2.2
15.5.4.3
15.5.4.3.1
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MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Ten-Bit Interface (TBI) .......................................................................................... 15-122
Hash Function Registers .................................................................................... 15-106
DMA Attribute Registers................................................................................... 15-108
Lossless Flow Control Configuration Registers ................................................ 15-109
Hardware Assist for IEEE1588 Compliant Timestamping................................ 15-110
TBI Transmit Process ........................................................................................ 15-122
TBI Receive Process.......................................................................................... 15-122
TBI MII Set Register Descriptions .................................................................... 15-123
Transmit Undersize Frame Counter (TUND)................................................ 15-100
Transmit Fragment Counter (TFRG)............................................................. 15-100
Carry Register 1 (CAR1) ............................................................................... 15-101
Carry Register 2 (CAR2) ............................................................................... 15-102
Carry Mask Register 1 (CAM1) .................................................................... 15-103
Carry Mask Register 2 (CAM2) .................................................................... 15-105
Receive Filer Rejected Packet Counter (RREJ) ............................................ 15-106
Individual/Group Address Registers 0–7 (IGADDRn) ................................. 15-107
Group Address Registers 0–7 (GADDRn) .................................................... 15-107
Attribute Register (ATTR)............................................................................. 15-108
Receive Queue Parameters 0–7 (RQPRM0–PQPRM7) ................................ 15-109
Receive Free Buffer Descriptor Pointer Registers 0–7
Timer Control Register (TMR_CTRL) ......................................................... 15-110
Timer Event Register (TMR_TEVENT) ....................................................... 15-112
Timer Event Mask Register (TMR_TEMASK) ............................................ 15-114
Timer PTP Packet Event Register (TMR_PEVENT) .................................... 15-115
Timer Event Mask Register (TMR_PEMASK) ............................................ 15-115
Timer Status Register (TMR_STAT) ............................................................. 15-116
Timer Counter Register (TMR_CNT_H/L)................................................... 15-117
Timer Drift Compensation Addend Register (TMR_ADD).......................... 15-117
Timer Accumulator Register (TMR_ACC)................................................... 15-118
Timer Prescale Register (TMR_PRSC)......................................................... 15-118
Timer Offset Register (TMROFF_H/L) ........................................................ 15-119
Alarm Time Comparator Register (TMR_ALARM1–2_H/L) ...................... 15-119
Timer Fixed Interval Period Register (TMR_FIPER1–3) ............................. 15-120
External Trigger Stamp Register (TMR_ETTS1–2_H/L) ............................. 15-121
Packet Encapsulation ..................................................................................... 15-122
8B10B Encoding............................................................................................ 15-122
Preamble Shortening...................................................................................... 15-122
Synchronization ............................................................................................. 15-123
Auto-Negotiation for 1000BASE-X.............................................................. 15-123
Control Register (CR).................................................................................... 15-124
(RFBPTR0–RFBPTR7) ............................................................................. 15-109
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