MPC8313CZQADDC Freescale Semiconductor, MPC8313CZQADDC Datasheet - Page 518

• Manufacturer Part Number: MPC8313CZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB NO EN EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CZQADDC

• Processor Series: MPC8313
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
When the core begins accessing memory after system reset, LCS0 is asserted initially to load a 4-Kbyte
boot block into the FCM buffer RAM, but core instruction fetches occur from the buffer RAM.
10.4.3.4.1
The boot chip-select also provides a programmable port size, which is configured during reset. The boot
chip-select does not provide write protection. LCS0 operates this way until the first write to OR0 and it
can be used as any other chip-select register after the preferred address range is loaded into BR0. After the
first write to OR0, the boot chip-select can be restarted only with a hardware reset.
the initial values of the boot bank in the memory controller.
10.4.3.4.2
If FCM is selected as the boot ROM controller from power-on-reset configuration, eLBC will
automatically load from bank 0 a single 4-Kbyte page of boot code into the FCM buffer RAM during
HRESET (see
the FCM buffer RAM, but must ensure that any further data read from the NAND Flash EEPROM is
transferred under software control in order to continue the bootstrap process.
Since OR0[AM] is initially cleared during reset, all CPU fetches to eLBC will access the FCM buffer
RAM, which appears in the memory map as a 4-Kbyte RAM. No NAND Flash spare regions are mapped
during boot, therefore only 4 Kbytes of contiguous, main region data, loaded from the first pages of the
boot block, are accessible in eLBC bank 0, as indicated in
10-70
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Section 4.3.2.2.4, “Boot ROM
FCM Bank 0 Reset Initialization
Boot Block Loading into the FCM Buffer RAM
Table 10-38. Boot Bank Field Values after Reset for FCM as Boot Controller
Register
OR0
BR0
BCTLD
DECC
MSEL
ATOM
CSCT
EHTR
TRLX
Field
PGS
CHT
SCY
CST
RST
WP
AM
BA
PS
V
Location”). The CPU can execute boot code directly from
0000_0000_0000_0000_0
0000_0000_0000_0000_0
From RCWH[ROMLOC]
From por_cfg_scy[1:3]
Figure
From 01
Setting
001
00
00
0
0
0
1
1
1
1
1
1
10-57.
Table 10-38
Freescale Semiconductor
describes