SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 94

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

Table 5-2
in register TFR. It also lists the priorities of trap service for those cases in which more
than one trap condition might be detected within the same instruction. After any reset
(hardware reset, software reset instruction SRST, or reset by watchdog timer overflow)
program execution starts at the reset vector at location 00’0000
priority over every other system activity and, therefore, have the highest priority (trap
priority III).
Software traps may be initiated to any vector location between 00’0000
A service routine entered via a software TRAP instruction is always executed on the
current CPU priority level which is indicated in bit field ILVL in register PSW. This means
that routines entered via the software TRAP instruction can be interrupted by all
hardware traps or higher level interrupt requests.
Table 5-2
Exception Condition
Reset Functions
Hardware Reset
Software Reset
Watchdog Timer Overflow
Class A Hardware Traps
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Class B Hardware Traps
Undefined Opcode
Protected Instruction Fault
Illegal Word Operand Access
Illegal Instruction Access
Illegal External Bus Access
Reserved
Software Traps
TRAP Instruction
User’s Manual
lists the vector locations for hardware traps and the corresponding status flags
Hardware Trap Summary
Trap
Flag
–
NMI
STKOF
STKUF
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
–
–
Trap
Vector
RESET
RESET
RESET
NMITRAP
STOTRAP
STUTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
–
–
5-4
Vector
Location
00’0000
00’0000
00’0000
00’0008
00’0010
00’0018
00’0028
00’0028
00’0028
00’0028
00’0028
[2C
Any
[00’0000
00’01FC
in steps
of 4
Interrupt and Trap Functions
H
H
- 3C
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
. Reset conditions have
]
-
] [0B
C164CM/C164SM
Trap
Number
00
00
00
02
04
06
0A
0A
0A
0A
0A
Any
[00
H
H
H
H
H
H
H
H
H
H
H
H
H
H
- 7F
- 0F
and 00’01FC
Derivatives
V1.0, 2002-02
H
H
]
] –
Trap
Prio
III
III
III
II
II
II
I
I
I
I
I
Current
CPU
Priority
H
.