SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 63

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

4.2
Because up to four different instructions are processed simultaneously, additional
hardware has been used in the C164CM to consider all causal dependencies which may
exist on instructions in different pipeline stages. This functionality is provided without a
loss of performance. This extra hardware (for ‘forwarding’ operand read and write
values) resolves most of the possible conflicts (such as multiple usage of buses) in a time
optimized way; thus, in most cases, the pipeline operates without being noticeable to the
user. However, there are some very rare circumstances in which the C164CM as a
pipelined machine requires attention by the programmer. In these cases, the delays
caused by pipeline conflicts can be used for other instructions in order to optimize
performance.
Context Pointer Updating
An instruction which calculates a physical GPR operand address via the Context Pointer
(CP) register is mostly incapable of using a new CP value, which has been updated by
an immediately preceding instruction. Thus, to ensure that the new CP value is used, at
least one instruction must be inserted between a CP-changing instruction and a
subsequent GPR-using instruction, as shown in the following example:
I
I
I
Data Page Pointer Updating
An instruction which calculates a physical operand address via a particular Data
Page Pointer (DPPn) register (n = 0 to 3), is mostly incapable of using a new DPPn
register value which has been updated by an immediately preceding instruction. Thus,
to ensure that the new DPPn register value is used, at least one instruction must be
inserted between a DPPn-changing instruction and a subsequent instruction which
implicitly uses DPPn via a long or indirect addressing mode, as shown in the following
example:
I
I
I
User’s Manual
n
n+1
n+2
n
n+1
n+2
:SCXT CP,#0FC00h
:…
:MOV
:MOV
:…
:MOV
Particular Pipeline Effects
R0,#dataX
DPP0,#4
DPP0:0000H,R1;move contents of R1 to
;select a new context
;must not be an instruction using a GPR
;write to GPR 0 in the new context
;select data page 4 via DPP0
;must not be an instruction using DPP0
;location 01’0000
;supposed segment is enabled
4-6
Central Processing Unit (CPU)
H
(in data page 4),
C164CM/C164SM
Derivatives
V1.0, 2002-02