SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 105

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

C164CM/C164SM
Derivatives
Interrupt and Trap Functions
5.3
Prioritization of Interrupt and PEC Service Requests
Interrupt and PEC service requests from all sources can be enabled so they are
arbitrated and serviced (if they win), or they may be disabled, so their requests are
disregarded and not serviced.
Enabling and disabling interrupt requests may be done via three mechanisms:
• Control Bits
• Priority Level
• ATOMIC and EXTended Instructions
Control Bits allow switching of each individual source “ON” or “OFF” so that it may
generate a request or not. The control bits (xxIE) are located in the respective interrupt
control registers. All interrupt requests may be enabled or disabled generally via bit IEN
in register PSW. This control bit is the “main switch” which selects if requests from any
source are accepted or not.
For a specific request to be arbitrated, the respective source’s enable bit and the global
enable bit must both be set.
The Priority Level automatically selects a certain group of interrupt requests to be
acknowledged and ignores all other requests. The priority level of the source that won
the arbitration is compared against the CPU’s current level and the source is serviced
only if its level is higher than the current CPU level. Changing the CPU level to a specific
value via software blocks all requests on the same or lower level. An interrupt source
assigned to level 0 will be disabled and will never be serviced.
The ATOMIC and EXTend instructions automatically disable all interrupt requests for
the duration of the following 1 … 4 instructions. This is useful for semaphore handling,
for example, and does not require to re-enable the interrupt system after the inseparable
instruction sequence (see
Chapter
22).
Interrupt Class Management
An interrupt class covers a set of interrupt sources with the same importance, i.e. the
same priority from the system’s viewpoint. Interrupts of the same class must not interrupt
each other. The C164CM supports this function with two features:
Classes with up to four members can be established by using the same interrupt priority
(ILVL) and assigning a dedicated group level (GLVL) to each member. This functionality
is built-in and handled automatically by the interrupt controller.
Classes with more than four members can be established by using a number of adjacent
interrupt priorities (ILVL) and the respective group levels (four per ILVL). Each interrupt
service routine within this class sets the CPU level to the highest interrupt priority within
the class. All requests from the same or any lower level are blocked now, i.e. no request
of this class will be accepted.
User’s Manual
5-15
V1.0, 2002-02