SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 31

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

C164CM/C164SM
Derivatives
Architectural Overview
Serial Channels
Serial communication with other microcontrollers, processors, terminals, or external
peripheral components is provided by two serial interfaces with different functionality: an
Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous
Serial Channel (SSC).
The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller
families and supports full-duplex asynchronous communication at up to 780 kbit/s and
half-duplex synchronous communication at up to 3.1 Mbit/s @ 25 MHz CPU clock.
A dedicated baud rate generator allows all standard baud rates to be set up without
oscillator tuning. Four separate interrupt vectors are provided for transmission,
reception, and error handling. In asynchronous mode, 8- or 9-bit data frames are
transmitted or received, preceded by a start bit and terminated by one or two stop bits.
For multiprocessor communication, a mechanism has been included to distinguish
address bytes from data bytes (8-bit data plus wake-up bit mode). In synchronous mode,
the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is
generated by the ASC0. The ASC0 always shifts the Least Significant Bit (LSB) first. A
loop back option is available for testing purposes.
Optional hardware error detection capabilities have been included to increase the
reliability of data transfers. A parity bit can be generated automatically on transmission
or can be checked on reception. Framing error detection allows data frames with missing
stop bits to be recognized. An overrun error will be generated, if the last character
received has not been read out of the receive buffer register at the time that reception of
a new character is complete.
The SSC supports full-duplex synchronous communication at up to 6.25 Mbit/s @
25 MHz CPU clock. It may be configured so that it interfaces with serially linked
peripheral components. A dedicated baud rate generator allows set up of all standard
baud rates without oscillator tuning. Three separate interrupt vectors are provided for
transmission, reception, and error handling.
The SSC transmits or receives characters of 2 … 16 bits length synchronously to a shift
clock which can be generated by the SSC (master mode) or by an external master (slave
mode). The SSC can start shifting with the LSB or with the Most Significant Bit (MSB)
and allows selection of shifting and latching clock edges as well as the clock polarity.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. Transmit and receive error supervise the correct handling
of the data buffer. Phase and baudrate error detect incorrect serial data.
User’s Manual
2-14
V1.0, 2002-02