SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 344
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SAF-C164SM
Manufacturer Part Number
SAF-C164SM
Description
16-Bit CMOS Microcontroller
Manufacturer
Infineon Technologies
Datasheet
1.SAF-C164SM.pdf
(470 pages)
- Current page: 344 of 470
- Download datasheet (6Mb)
19.2
The Control/Status Register (CSR) accepts general control settings for the module and
provides general status information.
CSR
Control/Status Register
Bit
INIT
IE
SIE
EIE
CPS
CCE
TM
User’s Manual
OFF
15
rh
B
WRN
14
rh
E
Function (Control Bits)
Initialization
Starts the initialization of the CAN controller, when set.
INIT is set
Interrupt Enable
Enables or disables interrupt generation from the CAN module via the signal
XINTR. Does not affect status updates.
Status Change Interrupt Enable
Enables or disables interrupt generation when a message transfer
(reception or transmission) is successfully completed or a CAN bus error is
detected (and registered in the status partition).
Error Interrupt Enable
Enables or disables interrupt generation on a change of bit BOFF or EWRN
in the status partition).
Clock Prescaler Control Bit
0:
1:
Configuration Change Enable
Allows or inhibits CPU access to the Bit Timing Register (BTR) and the
Interface Port Control bit field (IPC) in register PCIR.
Test Mode (must be ‘0’)
This bit must always be cleared when writing to the Control Register as this
bit controls a special test mode used for production testing only. During
normal operation, use of this test mode may lead to undesired behavior of
the device.
General Functional Description
13
-
r
Standard mode: the input clock is divided 2:1. The minimum
input frequency to achieve a baudrate of 1 Mbit/s is
Fast mode: the input clock is used directly 1:1. The minimum
input frequency to achieve a baudrate of 1 Mbit/s is
rwh
OK
RX
12
rwh
OK
TX
11
– after a reset
– when entering the busoff state
– by the application software
10
LEC
rwh
9
XReg (EF00
8
19-7
TM CCE
rw
7
H
)
rw
6
5
0
r
CPS EIE
rw
4
On-Chip CAN Interface
Reset Value: XX01
C164CM/C164SM
f
rw
3
CPU
f
CPU
= 16 MHz.
SIE
rw
2
= 8 MHz.
Derivatives
V1.0, 2002-02
rw
IE
1
INIT
rwh
0
H
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