SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 134

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

6.3
The C164CM provides an Oscillator Watchdog (OWD) which monitors the clock signal
fed to input XTAL1 of the on-chip oscillator (either with a crystal or via external clock
drive) in prescaler or direct drive mode (unless the PLL provides the basic clock). For
this operation, the PLL provides a clock signal (base frequency) which is used to
supervise transitions on the oscillator clock. This PLL clock is independent of the XTAL1
clock. When the expected oscillator clock transitions are missing, the OWD activates the
PLL Unlock / OWD interrupt node and supplies the CPU with the PLL clock signal instead
of the selected oscillator clock (see
oscillate with its base frequency.
In direct drive mode the PLL base frequency is used directly (
In prescaler mode, the PLL base frequency is divided by 2 (
If the oscillator clock fails while the PLL provides the basic clock, the system will be
supplied with the PLL base frequency anyway.
Using this PLL clock signal, the CPU can either execute a controlled shutdown sequence
bringing the system into a defined and safe idle state, or it can provide an emergency
operation of the system with reduced performance based on this (normally slower)
emergency clock.
Note: The CPU clock source is switched back to the oscillator clock only after a
The Oscillator Watchdog can be disabled by setting bit OWDDIS in register SYSCON.
In this case, the PLL remains idle and provides no clock signal, while the CPU clock
signal is derived directly from the oscillator clock or via prescaler or SDD. Also, no
interrupt request will be generated in case of a missing oscillator clock.
Note: At the end of an external reset, bit OWDDIS reflects the inverted level of pin RD
The oscillator watchdog cannot provide full security while the CPU clock signal is
generated by the SlowDown Divider because the OWD cannot switch to the PLL clock
in this case (see
available (for instance, the input frequency is too low or for intermittent failure only).
A broken crystal cannot be detected by software (OWD interrupt server) as no SDD clock
is available in such a case.
User’s Manual
hardware reset.
at that time. Thus, the Oscillator Watchdog may also be disabled via hardware by
(externally) pulling the RD line low upon a reset, in a manner similar to the
standard reset configuration via PORT0.
Oscillator Watchdog
Figure
6-4). OWD interrupts are only recognizable if
Figure
6-9
6-4). Under these circumstances, the PLL will
f
CPU
f
CPU
= 1 … 2.5 MHz).
= 2 … 5 MHz).
C164CM/C164SM
Clock Generation
Derivatives
V1.0, 2002-02
f
OSC
is still