SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 80

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

Bit
DPPxPN
The DPP registers are implicitly used whenever data accesses to any memory location
are made via indirect or direct long 16-bit addressing modes (except for override
accesses via EXTended instructions and PEC data transfers). After reset, the Data Page
Pointers are initialized in such a way that all indirect or direct long 16-bit addresses result
in identical 18-bit addresses. This allows access to data pages 3 … 0 within segment 0
as shown in
is required.
Data paging is performed by concatenating the lower 14 bits of an indirect or direct long
16-bit address with the contents of the DPP register selected by the upper two bits of the
16-bit address. The contents of the selected DPP register specify one of the 1024
possible data pages. This data page base address together with the 14-bit page offset
forms the physical 24-bit address (the selectable part is driven to the address pins).
In non-segmented memory mode, only the two least significant bits of the implicitly
selected DPP register are used to generate the physical address. Thus, extreme care
should be taken when changing the content of a DPP register if a non-segmented
memory model is selected to avoid unexpected results.
A DPP register can be updated via any instruction capable of modifying an SFR.
Note: Due to the internal instruction pipeline, a new DPP value is not yet usable for the
User’s Manual
operand address calculation of the instruction immediately following the
instruction which updates the DPP register.
Figure
Function
Data Page Number of DPPx
Specifies the data page selected via DPPx. Only the least significant two
bits of DPPx are significant, when segmentation is disabled.
4-6. If the user does not want to use data paging, no further action
4-23
Central Processing Unit (CPU)
C164CM/C164SM
Derivatives
V1.0, 2002-02