SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 367

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

C164CM/C164SM
Derivatives
On-Chip CAN Interface
19.4
Controlling the CAN Module
The CAN module is controlled by the C164CM via hardware signals (e.g. reset) and via
register accesses executed by software.
Accessing the On-Chip CAN Module
The CAN module is implemented as an X-Peripheral and is therefore accessed like an
external memory or peripheral. This means that the registers of the CAN module can be
read and written using 16-bit or 8-bit direct or indirect MEM addressing modes. Bit
handling is not supported via the XBUS. Since the XBUS, to which the CAN module is
connected, also represents the external bus, CAN accesses follow the same rules and
procedures as accesses to the external bus. CAN accesses cannot be executed in
parallel to external instruction fetches or data read/writes, but are arbitrated and inserted
into the external bus access stream.
Accesses to the CAN module use demultiplexed addresses, a 16-bit data bus (byte
accesses are possible), two waitstates, and no tristate waitstate.
The CAN address area starts at 00’EF00
and covers 256 Bytes. This area is decoded
H
internally, so none of the programmable address windows must be sacrificed in order to
access the on-chip CAN module.
The advantage of locating the CAN address area in segment 0 is that the CAN module
is accessible via data page 3. This is the ‘system’ data page, accessed usually through
the ‘system’ data page pointer DPP3. In this way, internal addresses (such like SFRs,
internal RAM, and the CAN registers), are all located within the same data page and form
a contiguous address space.
Power Down Mode
If the C164CM enters Power Down mode, the XCLK signal will be turned off. This stops
the operation of the CAN module; thus, any message transfer is interrupted. To ensure
that the CAN controller is not stopped while sending a dominant level (‘0’) on the CAN
bus, the CPU should set bit INIT in the Control Register prior to entering Power Down
mode. The CPU can determine if a transmission is in progress by reading bits TXRQ and
NEWDAT in the message objects and bit TXOK in the Control Register. After returning
from Power Down mode via hardware reset, the CAN module must be reconfigured.
User’s Manual
19-30
V1.0, 2002-02