SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 422
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SAF-C164SM
Manufacturer Part Number
SAF-C164SM
Description
16-Bit CMOS Microcontroller
Manufacturer
Infineon Technologies
Datasheet
1.SAF-C164SM.pdf
(470 pages)
- Current page: 422 of 470
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22
A number of features have been incorporated into the instruction set of the C164CM, to
facilitate software development, including constructs for modularity, loops, and context
switching. In many cases, commonly used instruction sequences have been simplified
while their flexibility has been enhanced. The following programming features help to
fully utilize this instruction set.
Instructions Provided as Subsets of Instructions
In many cases, instructions found in other microcontrollers are provided as subsets of
more powerful instructions in the C164CM. This allows the same functionality to be
provided while decreasing the hardware required and decreasing decode complexity. To
assist with assembly programming, these instructions which are familiar from other
microcontrollers, can be built in macros, thus providing the same names.
Direct Substitution Instructions are instructions known from other microcontrollers
which can be replaced by the following instructions of the C164CM:
Table 22-1
Substituted Instruction
CLR
CPLB
DEC
INC
SWAPB
Modification of System Flags is performed using bit set or bit clear instructions
(BSET, BCLR). All bit and word instructions can access the PSW register, so instructions
such as CLEAR CARRY or ENABLE INTERRUPTS are not required.
External Memory Data Access does not require special instructions to load data
pointers or explicitly load and store external data. The C164CM provides a Von
Neumann memory architecture and its on-chip hardware automatically detects accesses
to internal RAM, GPRs, and SFRs.
Multiplication and Division
Multiplication and division of words and double words are provided through multiple
cycle instructions implementing a Booth algorithm. Each instruction implicitly uses the
32-bit register MD (MDL = lower 16 bits, MDH = upper 16 bits). The MDRIU flag (Multiply
or Divide Register In Use) in register MDC is set whenever either half of this register is
written to or when a multiply/divide instruction is started. It is cleared whenever the MDL
User’s Manual
System Programming
Substitution of Instructions
Rn
Bit
Rn
Rn
Rn
C164CM Instruction
AND
BMOVN
SUB
ADD
ROR
22-1
Rn, #0
Bit, Bit
Rn, #1
Rn, #1
Rn, #8
H
H
H
H
Function
Clear register
Complement bit
Decrement register
Increment register
Swap bytes within word
System Programming
C164CM/C164SM
Derivatives
V1.0, 2002-02
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