SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 181

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

C164CM/C164SM
Derivatives
External Bus Interface
Programmable Memory Tri-State Time
The C164CM allows the user to adjust the time between two subsequent external
accesses to account for the tri-state time of the external device. The tri-state time defines
when the external device releases the bus after deactivation of the read command (RD).
Bus Cycle
ALE
BUS (P0)
Data/Instr.
Address
RD
MTTC Wait State
MCT02065M
Figure 9-8
Memory Tri-State Time
The output of the next address on the external bus can be delayed for a memory or
peripheral which needs more time to switch off its bus drivers. This is accomplished by
introducing a wait state after the previous bus cycle (see
Figure
9-8). During this
memory tri-state time wait state, the CPU is not idle, so CPU operations will be slowed
down only if a subsequent external instruction or data fetch operation is required during
the next instruction cycle.
The memory tri-state time waitstate requires one CPU clock (2 TCL) and is controlled via
the MTTCx bits of the BUSCON registers. A waitstate will be inserted if bit MTTCx is ‘0’
(default after reset).
Note: External bus cycles in multiplexed bus modes implicitly add one tri-state time
waitstate in addition to the programmable MTTC waitstate.
User’s Manual
9-12
V1.0, 2002-02