SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 439

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

C164CM/C164SM
Derivatives
System Programming
22.11
Pits, Traps, and Mines
Although handling the internal code memory provides a powerful means of enhancing
the overall performance and flexibility of a system, extreme care must be taken to avoid
a system crash. Instruction memory is the most crucial resource for the C164CM and it
must be ensured that it never runs out. The following precautions help to take advantage
of the methods mentioned above without jeopardizing system security.
Internal code memory access after reset: When the first instructions are to be fetched
from internal memory (EA = ‘1’), the device must contain code memory containing a valid
reset vector and valid code at its destination.
Mapping the internal ROM area to segment 1: Due to instruction pipelining, any new
ROM mapping will at the earliest become valid for the second instruction after the
instruction which has changed the ROM mapping. To enable accesses to the ROM area
after mapping a branch to the newly selected ROM area (JMPS) and reloading of all data
page pointers is required.
This also applies to re-mapping the internal ROM area to segment 0.
Enabling the internal code memory after reset: When enabling the internal code
memory after having booted the system from external memory, note that the C164CM
will then access the internal memory using the current segment offset, rather than
accessing external memory.
Disabling the internal code memory after reset: When disabling the internal code
memory after having booted the system from there, note that the C164CM will not
access external memory before a jump to segment 0 (in this case) is executed.
General Rules
When mapping the code memory no instruction or data accesses should be made to the
internal memory, otherwise unpredictable results may occur.
To avoid these problems, the instructions which configure the internal code memory
should be executed from external memory or from the on-chip RAM.
Whenever the internal code memory is disabled, enabled, or remapped, the DPPs must
be explicitly (re)loaded to enable correct data accesses to the internal and/or external
memory.
User’s Manual
22-18
V1.0, 2002-02