SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 236

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

The shift register of the SSC is connected to both the transmit pin and the receive pin via
the pin control logic (see block diagram). Transmission and reception of serial data is
synchronized and simultaneous: the same number of bits are transmitted and received.
The major steps of the state machine of the SSC are controlled by the shift clock signal
(see
In master mode (SSCMS = ‘1’) two clocks per bit-time are generated, each upon an
underflow of the baudrate counter.
In slave mode (SSCMS = ‘0’) one clock per bit-time is generated, when the latching
edge of the external SCLK signal has been detected.
Transmit data is written into the transmit buffer SSCTB. When the contents of the buffer
are moved to the shift register (immediately if no transfer is currently active) a transmit
interrupt request (SSCTIR) is generated indicating that SSCTB may be reloaded again.
The busy flag SSCBSY is set when the transfer starts (with the next following shift clock
in master mode, immediately in slave mode).
Note: If no data is written to SSCTB prior to a slave transfer, this transfer starts after the
When the contents of the shift register are moved to the receive buffer SSCRB after the
programmed number of bits (2 … 16) have been transferred, i.e. after the last latching
edge of the current transfer, a receive interrupt request (SSCRIR) is generated.
The busy flag SSCBSY is cleared at the end of the current transfer (with the next
following shift clock in master mode, immediately in slave mode).
When the transmit buffer is not empty at that time (in the case of continuous transfers)
the busy flag is not cleared and the transfer goes on after moving data from the buffer to
the shift register.
Software should not modify SSCBSY, as this flag is hardware controlled.
Note: Only one SSC (etc.) can be master at a given time.
The transfer of serial data bits can be programmed in many respects:
• Data width can be chosen from 2 bits to 16 bits
• Transfer may start with the LSB or the MSB
• Shift clock may be idle low or idle high
• Data bits may be shifted with the leading or trailing edge of the clock signal
• Baudrate may be set within a wide range (see baudrate generation)
• Shift clock may be generated (master) or received (slave)
This flexibility allows adaptation of the SSC to a wide range of applications which require
serial data transfer.
User’s Manual
Figure
first latching edge of the external SCLK signal is detected. No transmit interrupt is
generated in this case.
12-2).
12-5
High-Speed Synchronous Serial Interface
C164CM/C164SM
Derivatives
V1.0, 2002-02