SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 43

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

Note: The upper 256 Bytes of the SFR area, the ESFR area, and the Internal RAM are
Code accesses are always made on even byte addresses. The highest possible code
storage location in the Internal RAM is either 00’FDFE
00’FDFC
instruction (unconditional), because sequential boundary crossing from Internal RAM to
the SFR area is not supported and causes erroneous results.
Any word and byte data in the Internal RAM can be accessed via indirect or long 16-bit
addressing modes, if the selected DPP register points to data page 3. Any word data
access is made on an even byte address. The highest possible word data storage
location in the internal RAM is 00’FDFE
be accessed independent of the contents of the DPP registers via the PEC source and
destination pointers.
The upper 256 Bytes of the Internal RAM (00’FD00
of the current bank are provided for single bit storage, and thus they are bit-addressable.
System Stack
The system stack may be defined within the Internal RAM. The size of the system stack
is controlled by bitfield STKSZ in register SYSCON (see
Table 3-1
<STKSZ>
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
For all system stack operations the on-chip RAM is accessed via the Stack Pointer (SP)
register. The stack grows downward from higher towards lower RAM address locations.
Only word accesses are supported to the system stack. A stack overflow (STKOV)
register and a stack underflow (STKUN) register are provided to control the lower and
upper limits of the selected stack area. These two stack boundary registers can be used
both for protection against data destruction and for implementation of a circular stack
with hardware-supported system stack flushing and filling (except for option ‘111’). The
technique for implementing the circular stack is described in
User’s Manual
B
B
B
B
B
B
B
B
bit-addressable (see shaded blocks in
H
for double word instructions. The respective location must contain a branch
Stack Size (words) Internal RAM Addresses (words)
256
128
64
32
512
–
–
1024
System Stack Size Encoding
00’FBFE
00’FBFE
00’FBFE
00’FBFE
00’FBFE
Reserved. Do not use this combination.
Reserved. Do not use this combination.
00’FDFE
H
. For PEC data transfers, the internal RAM can
3-5
H
H
H
H
H
H
Figure
… 00’FA00
… 00’FB00
… 00’FB80
… 00’FBC0
… 00’F800
… 00’F600
H
3-3).
through 00’FDFF
H
Table
H
H
for single word instructions or
H
H
H
H
(Note: No circular stack)
(Default after Reset)
Chapter
3-1).
Memory Organization
C164CM/C164SM
22.
H
) and the GPRs
Derivatives
V1.0, 2002-02