SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 148

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

and segment addresses. Software can read this register in order to react according to
the selected configuration, if required.
When the reset is terminated, the internal pull-up devices are switched off, and PORT0
will be switched to the appropriate operating mode.
During external accesses in multiplexed bus modes, PORT0 first outputs the 16-bit
intra-segment address as an alternate output function. PORT0 is then switched to
high-impedance input mode to read the incoming instruction or data. In 8-bit data bus
mode, two memory cycles are required for word accesses, the first for the low byte and
the second for the high byte of the word. During write cycles, PORT0 outputs the data
byte or word after outputting the address.
During external accesses in demultiplexed bus modes PORT0 reads the incoming
instruction or data word or outputs the data byte or word.
While external bus cycles are executed, PORT0 is controlled by the bus controller. The
port direction is determined by the type of the bus cycle, the data are transferred directly
from/to the bus controller hardware. The alternate output data can be the 16-bit
intrasegment address or the 8/16-bit data information. While PORT0 is not used by the
bus controller, it is controlled by its direction and output latch registers. User software
must therefore be very careful when writing to PORT0 registers while the external bus is
enabled. In most cases keeping the reset values will be the best choice.
The upper 5 pins of PORT0 additionally provide the interface lines for the serial
interfaces SSC (SCLK, MTSR, MRST) and ASC0 (RxD0, TxD0). The output lines are
ANDed with the respective port output latches (as it is in Port 3 of other controllers).
In 8-bit multiplexed address mode PORT0 only drives 11 address lines (A10 … AD0).
This reduces the external address space to 2 KBytes, but frees the interface pins for the
serial interfaces ASC0 and SSC. In this case the AltEN lines for the upper 5 pins are not
activated, i.e. the EBC does not control these pins.
Table 7-3
PORT0 Pin(s) Alternate Function (8-Bit MUX)
P0H.7
P0H.6
P0H.5
P0H.4
P0H.3
P0H.2-0
P0L.7-0
User’s Manual
Alternate Functions of PORT0
SCLK
MTSR
MRST
RxD0
TxD0
A10-8
AD7-0
SSC Shift Clock Input/Output
SSC Master Transmit / Slave Receive
SSC Master Receive / Slave Transmit
ASC0 Receive Data Input
ASC0 Transmit Data Output
Upper three Address Lines
Address/Data Lines
7-13
C164CM/C164SM
Altern. Function
(Others)
AD15
AD14
AD13
AD12
AD11
AD10-8
AD7-0
Parallel Ports
Derivatives
V1.0, 2002-02