SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 44

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

General Purpose Registers
The General Purpose Registers (GPRs) use a block of 16 consecutive words within the
Internal RAM. The Context Pointer (CP) register determines the base address of the
currently active register bank. This register bank may consist of up to 16 Word-GPRs
(R0, R1, … R15) and/or of up to 16 Byte-GPRs (RL0, RH0, … RL7, RH7). The sixteen
Byte-GPRs are mapped onto the first eight Word-GPRs (see
In contrast to the system stack, a register bank grows from lower towards higher address
locations and occupies a maximum space of 32 Bytes. The GPRs are accessed via short
2-, 4-, or 8-bit addressing modes using the Context Pointer (CP) register as base
address (independent of the current DPP register contents). Additionally, each bit in the
currently active register bank can be accessed individually.
Table 3-2
Internal RAM Address
<CP> + 1E
<CP> + 1C
<CP> + 1A
<CP> + 18
<CP> + 16
<CP> + 14
<CP> + 12
<CP> + 10
<CP> + 0E
<CP> + 0C
<CP> + 0A
<CP> + 08
<CP> + 06
<CP> + 04
<CP> + 02
<CP> + 00
The C164CM supports fast register bank (context) switching. Multiple register banks can
physically exist within the Internal RAM at the same time. Only the register bank selected
by the Context Pointer register (CP) is active at a given time, however. Selecting a new
active register bank is done simply by updating the CP register. A particular Switch
Context (SCXT) instruction performs register bank switching and automatically saves
User’s Manual
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Mapping of General Purpose Registers to RAM Addresses
Byte Registers
–
–
–
–
–
–
–
–
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
RL7
RL6
RL5
RL4
RL3
RL2
RL1
RL0
3-6
Word Register
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Table
Memory Organization
C164CM/C164SM
3-2).
Derivatives
V1.0, 2002-02