SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 220

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

S0PE will be set along with the error interrupt request flag, if a wrong parity bit is
received. The parity bit itself will be stored in bit S0RBUF.7.
Figure 11-3 Asynchronous 8-bit Data Frames
9-bit data frames consist of either 9 data bits D8 … D0 (S0M = ‘100
D7 … D0 plus an automatically generated parity bit (S0M = ‘111
D7 … D0 plus a wake-up bit (S0M = ‘101
bit S0ODD in register S0CON. An even parity bit will be set, if the modulo-2-sum of the
8 data bits is ‘1’. An odd parity bit will be cleared in this case. Parity checking is enabled
via bit S0PEN (always OFF in 9-bit data and wake-up modes). The parity error flag S0PE
will be set along with the error interrupt request flag if a wrong parity bit is received. The
parity bit itself will be stored in bit S0RBUF.8.
In wake-up mode, received frames are transferred to the receive buffer register only if
the 9
activated and no data will be transferred.
This feature may be used to control communication in a multi-processor system: When
the master processor wants to transmit a block of data to one of several slaves, it first
sends out an address byte which identifies the target slave. An address byte differs from
a data byte in that the additional 9
byte, so that no slave will be interrupted by a data ‘byte’. An address ‘byte’ will interrupt
all slaves (operating in 8-bit data + wake-up bit modes), so each slave can examine the
8 LSBs of the received character (the address). The addressed slave will switch to 9-bit
data mode (for example, by clearing bit S0M.0), which enables it to also receive the data
bytes that will be coming (having the wake-up bit cleared). The slaves not being
addressed remain in 8-bit data + wake-up bit modes, ignoring the following data bytes.
Figure 11-4 Asynchronous 9-bit Data Frames
User’s Manual
th
Start
bit (the wake-up bit) is ‘1’. If this bit is ‘0’, no receive interrupt request will be
Bit
Start
Bit
(LSB)
D0
(LSB)
D0
D1
D1
D2
D2
D3
th
D3
bit is a ‘1’ for an address byte and a ‘0’ for a data
D4
Asynchronous/Synchronous Serial Interface
B
11-6
D4
’). Parity may be odd or even, depending on
D5
D5
D6
D6
D7
Parity
D7 /
9th
Bit
(1st)
Stop
Bit
C164CM/C164SM
Stop
Data Bit D8
Parity
Wake-up Bit
(1st)
Bit
B
’), or 8 data bits
Stop
2nd
B
Bit
Stop
’), 8 data bits
Derivatives
2nd
Bit
V1.0, 2002-02
MCT04377
MCT04378