SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 280

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

16.5
The compare modes allow triggering of events (interrupts and/or output signal
transitions) with minimum software overhead. In all compare modes, the 16-bit value
stored in compare register CCx (in the following also referred to as ‘compare value’) is
continuously compared with the contents of the allocated timer (T7 or T8). If the current
timer contents match the compare value, an appropriate output signal, based on the
selected compare mode, can be generated at the corresponding output pin CCxIO and
the associated interrupt request flag CCxIR is set, which can generate an interrupt
request (if enabled). See
As for capture mode, the compare registers are also processed sequentially in compare
mode. When any two compare registers are programmed to the same compare value,
their corresponding interrupt request flags will be set to ‘1’ and the selected output
signals will be generated within eight CPU clock cycles after the allocated timer is
incremented to the compare value. Further compare events on the same compare value
are disabled
reset, compare events for register CCx will become enabled only if the allocated timer
has been incremented or written to by software and one of the compare modes
described in the following sections has been selected for this register.
The different compare modes which can be programmed for a given compare register
CCx are selected by the mode control field CCMODx in the associated capture/compare
mode control register. Each of the compare modes, including the special ‘double
register’ mode, is discussed in detail in the following sections.
Compare Mode 0
This is an interrupt-only mode which can be used for software timing purposes. Compare
mode 0 is selected for a given compare register CCx by setting bit field CCMODx of the
corresponding mode control register to ‘100
In this mode, the interrupt request flag CCxIR is set each time a match is detected
between the contents of compare register CCx and the allocated timer. Several of these
compare events are possible within a single timer period, when the compare value in
register CCx is updated during the timer period. The corresponding port pin CCxIO is not
affected by compare events in this mode and can be used as general purpose IO pin.
If compare mode 0 is programmed for one of the registers CC24 … CC27, the
double-register compare mode becomes enabled for this register if the corresponding
bank 1 register is programmed to compare mode 1 (see
Mode” on Page
1)
User’s Manual
Compare events are detected sequentially, where a sequence (checking 8 times 2 channels each) takes
8 CPU clock cycles. Even if more sequences are executed before the timer increments (lower timer frequency)
a given compare value only results in one single compare event.
Compare Modes
1)
until the timer is incremented again or is written to by software. After a
16-19).
Section 16.7
for a possible solution for channels 28 … 31.
16-14
B
’.
Capture/Compare Unit CAPCOM2
“Double-Register Compare
C164CM/C164SM
Derivatives
V1.0, 2002-02