SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 294
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SAF-C164SM
Manufacturer Part Number
SAF-C164SM
Description
16-Bit CMOS Microcontroller
Manufacturer
Infineon Technologies
Datasheet
1.SAF-C164SM.pdf
(470 pages)
- Current page: 294 of 470
- Download datasheet (6Mb)
17.2
The compare timer counts up starting at 0000
respective compare value in register CC6x the associated output signal is switched to
its active state. Upon reaching the period value stored in register TxP the timer is cleared
and repeats counting up. At this time also the output signals are switched to their passive
state.
In
CC6x and/or COUT6x.
Figure 17-4 Operation in Edge Aligned Mode
The example above shows how to generate PWM output signals with duty cycles
between 0% and 100%, including the corner values. The duty cycle directly corresponds
to the programmed compare value. The indicated output signals can be output on the
respective pin CC6x or COUT6x, or both. The pin allocation is controlled via bitfields
CMSELx in register CC6MSEL. Register CC6MCON selects the passive level for
enabled outputs. The example above uses active high signals: the passive level is low
(the associated select bit is ‘0’).
User’s Manual
Figure 17-4
CC
CCP = period value in register T12P T13P
*)
*)
CCP = 7
T12OF = 0
T12 Start
(CC = 0)
(CC = 1)
(CC = 4)
(CC = 7)
(CC
= compare value in registers CC6x
Output signal at pin CC6x or COUT6x selected as active high.
For an active low output the signals would appear inverted.
Edge Aligned Mode
7)
the selected edge offset is zero, therefore the output signal refers to
T12 Value
"0"
0
1
2
3
4
5
6
7
17-5
0
1
2
H
. When the timer contents match the
3
Capture/Compare Unit CAPCOM6
4
5
6
7
0
1
C164CM/C164SM
2
3
4
MCT04111
Derivatives
V1.0, 2002-02
Duty
Cycles:
100%
87.5%
50%
12.5%
0%
Time
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