SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 435

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

22.8
The instructions of the C164CM are very efficient (most instructions execute in one
machine cycle). Even the multiplication and division are interruptible in order to minimize
the response latency to interrupt requests (internal and external). This is vital in many
microcontroller applications.
Some special occasions, however, require certain code sequences (such as semaphore
handling) to be executed uninterruptedly to function properly. This can be accomplished
by inhibiting interrupts during the respective code sequence by disabling and enabling
them before and after the sequence. The necessary overhead may be reduced by
means of the ATOMIC instruction which allows locking 1 … 4 instructions to an
inseparable code sequence, during which the interrupt system (standard interrupts and
PEC requests) and Class A Traps (NMI, stack overflow/underflow) are disabled. Class
B Traps (illegal opcode, illegal bus access, etc.), however, will interrupt the atomic
sequence, since it indicates a severe hardware problem.
The interrupt inhibit caused by an ATOMIC instruction gets active immediately; no other
instruction will enter the pipeline except the one following the ATOMIC instruction, and
no interrupt request will be serviced in between. All instructions requiring multiple cycles
or hold states are regarded as one instruction in this case (for example, MUL is one
instruction). Any instruction type can be used within an inseparable code sequence.
ATOMIC
MOV
MOV
MUL
MOV
Note: As long as any Class B trap is pending (any of the class B trap flags in register
22.9
The standard mechanism for accessing data locations uses one of the four data page
pointers (DPPx), which selects a 16-KByte data page, and a 14-bit offset within this data
page. The four DPPs allow immediate access to up to 64 KBytes of data. In applications
with large data arrays, especially in HLL applications using large memory models, this
may require frequent reloading of the DPPs, even for single accesses.
User’s Manual
TFR is set) the ATOMIC instruction will not work. Clear the respective B trap flag
at the beginning of a B trap routine if ATOMIC shall be used within the routine.
Inseparable Instruction Sequences
#3
R0, #1234H
R1, #5678H
R0, R1
R2, MDL
Overriding the DPP Addressing Mechanism
;The next 3 instr. are locked (No NOP requ.)
;Instr. 1 (no other instr. enters pipeline!)
;Instr. 2
;Instr. 3: MUL regarded as one instruction
;This instruction is out of the scope …
;… of the ATOMIC instruction sequence
22-14
System Programming
C164CM/C164SM
Derivatives
V1.0, 2002-02