SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 133

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

Table 6-1
RP0H.7-5
(P0H.7-5)
1)
2)
The PLL constantly synchronizes to the external clock signal. Due to the fact that the
external frequency is 1/F’th of the PLL output frequency, the output frequency may be
slightly higher or lower than the desired frequency. This jitter is irrelevant for longer time
periods. For short periods (1 … 4 CPU clock cycles), it remains below 4%.
Figure 6-6
User’s Manual
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
The external clock input range refers to a CPU clock range of 10 … 25 MHz.
The maximum frequency depends on the duty cycle of the external clock signal. In emulation mode pin P0.15
(P0H.7) is inverted, i.e. the configuration ‘111’ would select direct drive in emulation mode.
f
IN
CPU Frequency
f
C164CM Clock Generation Modes
PLL Block Diagram
CPU
f
f
OSC
OSC
f
f
f
f
f
f
OSC
OSC
OSC
OSC
OSC
OSC
=
Reset
PWRDN
f
OSC
/ 2
1.5
2.5
4
3
2
5
1
F
External Clock
Input Range
2.5 to 6.25 MHz
3.33 to 8.33 MHz
5 to 12.5 MHz
2 to 5 MHz
1 to 25 MHz
6.66 to 16.6 MHz
2 to 50 MHz
4 to 10 MHz
Reset
Sleep
f
PLL Circuit
PLL
XP3INT
Lock
= F ×
6-8
1)
f
IN
(RP0H.7-5)
F
CLKCFG
Notes
Default configuration
–
–
–
Direct drive
–
CPU clock via prescaler
–
f
PLL
OWD
2)
C164CM/C164SM
Clock Generation
MCB04339
f
Derivatives
CPU
V1.0, 2002-02