SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 121

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

5.9
Traps interrupt current execution in a manner similar to standard interrupts. However,
trap functions offer the possibility to bypass the interrupt system’s prioritization process
for cases in which immediate system reaction is required. Trap functions are not
maskable and always have priority over interrupt requests on any priority level.
The C164CM provides two different kinds of trapping mechanisms: Hardware Traps are
triggered by events that occur during program execution (such as illegal access or
undefined opcode); Software Traps are initiated via an instruction within the current
execution flow.
Software Traps
The TRAP instruction causes a software call to an interrupt service routine. The trap
number specified in the operand field of the trap instruction determines which vector
location in the address range from 00’0000
Executing a TRAP instruction causes an effect similar to the occurrence of an interrupt
at the same vector. PSW, CSP (in segmentation mode), and IP are pushed on the
internal system stack and a jump is taken to the specified vector location. When
segmentation is enabled and a trap is executed, the CSP for the trap service routine is
set to code segment 0. No Interrupt Request flags are affected by the TRAP instruction.
The interrupt service routine called by a TRAP instruction must be terminated with a
RETI (return from interrupt) instruction to ensure correct operation.
Note: The CPU level in register PSW is not modified by the TRAP instruction, so the
Hardware Traps
Hardware traps are issued by faults or specific system states which occur during runtime
of a program (not identified at assembly time). A hardware trap may also be triggered
intentionally, for example: to emulate additional instructions by generating an Illegal
Opcode trap. The C164CM distinguishes eight different hardware trap functions. When
a hardware trap condition has been detected, the CPU branches to the trap vector
location for the respective trap condition. Depending on the trap condition, the instruction
which caused the trap is either completed or cancelled (i.e. it has no effect on the system
state) before the trap handling routine is entered.
Hardware traps are non-maskable and always have priority over every other CPU
activity. If several hardware trap conditions are detected within the same instruction
cycle, the highest priority trap is serviced (see
User’s Manual
service routine is executed on the same priority level from which it was invoked.
Therefore, the service routine entered by the TRAP instruction can be interrupted
by other traps or higher priority interrupts, other than when triggered by a
hardware trap.
Trap Functions
5-31
H
through 00’01FC
Table
5-2).
Interrupt and Trap Functions
H
will be branched to.
C164CM/C164SM
Derivatives
V1.0, 2002-02