SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 407

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

21.4
A separate clock path can be selected for Slow Down operation, bypassing the basic
clock path used for standard operation. The programmable Slow Down Divider (SDD)
divides the oscillator frequency by a factor of 1 … 32 which is specified via bitfield
CLKREL in register SYSCON2 (factor = <CLKREL>+1). When bitfield CLKREL is written
during SDD operation, the reload counter will output one more clock pulse with the “old”
frequency in order to resynchronize internally before generating the “new” frequency.
If direct drive mode is configured, clock signal
mode is configured, clock signal
examples below).
Figure 21-3 Slow Down Divider Operation
Using a 5 MHz input clock, for example, the on-chip logic may be run at a frequency
down to 156.25 kHz (or 78 kHz) without an external hardware change. An implemented
PLL may be switched off in this case or may continue running, depending on the
requirements of the application (see
Note: During Slow Down operation, the entire device (including bus interface and
User’s Manual
generation of signals CLKOUT or FOUT) is clocked with the SDD clock (see
Figure
f
f
OSC
SDD
Slow Down Operation
Factor = 3, Direct Drive
Factor = 5, Direct Drive
Factor = 3, Prescaler
21-3).
f
OSC
f
DD
is additionally divided by 2:1 to generate
Table
Reload Counter
CLKREL
21-11
21-2).
f
DD
is directly fed to
f
SDD
Power Management
C164CM/C164SM
f
CPU
Derivatives
MCD04477
. If prescaler
V1.0, 2002-02
f
CPU
(see