SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 312

• Manufacturer Part Number: SAF-C164SM
• Description: 16-Bit CMOS Microcontroller
• Manufacturer: Infineon Technologies

CTCON
Compare Timer Control Reg.
Bit
CTnCLK
CTnR
CTnRES
STE12
User’s Manual
CT13
rwh
15
P
ECT
13O
14
rw
STE
rwh
13
13
Function
Compare Timer Tn Input Clock Select
Selects the input clock for timer T12 or T13 derived from the CPU clock:
f
000:
…
111:
Compare Timer Tn Run Bit
CTnR starts and stops timer Tn (T12 or T13).
Together with bit CTnRES it controls Tn’s operation.
0:
1:
Compare Timer Tn Reset Control
0:
1:
Note: For capture mode (T12 only): Clearing CT12R after a capture
Timer T12 Shadow Latch Transfer Enable
0:
1:
Note: STE12 is cleared by hardware after the shadow latch transfer.
Tx
CT13
RES
12
rw
=
f
CPU
f
f
Timer Tn stops counting. If bit CTnRES = ‘1’ timer Tn is cleared
and the compare outputs are set to their defined idle state.
Timer Tn starts counting from its current value.
No effect on timer Tn when it is stopped.
Timer Tn is cleared when it is stopped and
the compare outputs are set to their defined idle state.
Transfer from the shadow latches to the initial value bits, and the
period, compare, and offset registers (T12P, CC6x, T12OF) of
timer T12 is disabled.
Timer T12’s initial value bits, and the period, compare, and offset
registers are loaded from their shadow latches when T12 reaches
0000
aligned mode).
In center aligned mode the registers are also loaded when T12
reaches the period value.
event while CT12RES = ‘1’ will destroy the value stored in the
capture register CC6x (all shadow registers are transparent).
Keep CT12RES = ‘0’ in capture mode.
Tx
Tx
CT13
11
rw
R
=
=
/ 2
H
f
f
CPU
CPU
<CTnCLK>
(cleared in edge aligned mode, counting down in center
10
CT13CLK
/ 128
rw
SFR (FF30
9
.
8
17-23
CTM ETRP STE
rw
7
H
/98
H
rw
Capture/Compare Unit CAPCOM6
6
)
rwh
12
5
CT12
RES
rw
4
CT12
Reset Value: 1010
C164CM/C164SM
rw
R
3
2
Derivatives
CT12CLK
V1.0, 2002-02
rw
1
0
H