SAF-C164SM Infineon Technologies, SAF-C164SM Datasheet - Page 184
![no-image](/images/manufacturer_photos/0/3/327/infineon_technologies_sml.jpg)
SAF-C164SM
Manufacturer Part Number
SAF-C164SM
Description
16-Bit CMOS Microcontroller
Manufacturer
Infineon Technologies
Datasheet
1.SAF-C164SM.pdf
(470 pages)
- Current page: 184 of 470
- Download datasheet (6Mb)
9.4
A set of registers controls the functions of the EBC. General features such as
segmentation and internal ROM mapping are controlled via register SYSCON. Bus cycle
properties such as length of ALE, external bus mode, read/write delay, and waitstates
are controlled via registers BUSCON4 … BUSCON0. Four of these registers (BUSCON4
… BUSCON1) have an address select register (ADDRSEL4 … ADDRSEL1) associated
with them. This allows specifying up to four address areas and the individual bus
characteristics within these areas. All accesses not covered by these four areas are then
controlled via BUSCON0. This allows memory components or peripherals to be used
with different interfaces within the same system while optimizing accesses to each of
them.
SYSCON
System Control Register
Bit
VISIBLE
XPEN
BDRSTEN Bidirectional Reset Enable Bit
OWDDIS
CLKEN
User’s Manual
15
STKSZ
14
rw
Controlling the External Bus Controller
13
Function
Visible Mode Control
0:
1:
XBUS Peripheral Enable Bit
0:
1:
0:
1:
Oscillator Watchdog Disable Bit
0:
1:
System Clock Output Enable (CLKOUT)
0:
1:
ROM
S1
12
rw
Accesses to XBUS peripherals are done internally.
XBUS peripheral accesses are made visible on the external pins.
Accesses to the on-chip X-Peripherals and their functions are
disabled.
The on-chip X-Peripherals are enabled and can be accessed.
Pin RSTIN is an input only.
Pin RSTIN is pulled low during the internal reset sequence
after any reset.
The on-chip oscillator watchdog is enabled and active.
The on-chip oscillator watchdog is disabled and the CPU clock is
always fed from the oscillator input.
CLKOUT disabled: pin may be used for general purpose IO or
for signal FOUT.
CLKOUT enabled: pin outputs the system clock signal.
SGT
DIS
11
rw
ROM
rwh
EN
10
SFR (FF12
9
-
-
CLK
EN
rw
8
9-15
7
H
-
-
/89
H
6
-
-
)
5
-
-
OWD
DIS
rwh
4
External Bus Interface
RST
Reset Value: 0XX0
BD
C164CM/C164SM
EN
rw
3
XPEN VISI-
rw
2
Derivatives
V1.0, 2002-02
BLE
rw
1
0
-
-
H
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