SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 96

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programming the Peripherals
Configuring interrupts requires two steps:
Events that change bits in the peripheral control registers can then trigger the interrupt.
Depending on the peripheral, from two to six peripheral interrupt sources are available to the
programmer.
Example 5-2 shows a short interrupt programmed for the HI08. The main program enables the
Host Receive Interrupt in the Host Control Register (HCR). When the interrupt is triggered
during code execution, the core processing jumps to the Host Receive Interrupt routine location
at p:$60 and executes the code there. Since this is a short interrupt, the core returns to normal
code execution after executing the two move instructions, and an RTI instruction is not
necessary.
; Short Interrupt Routine
5.4.3 DMA
The Direct Memory Access (DMA) controller permits data transfers between internal/external
memory and/or internal/external I/O in any combination without the intervention of the
DSP56303 core. Dedicated DMA address and data buses and internal memory partitioning
ensure that a high level of isolation is achieved so the DMA operation does not interfere with the
core operation or slow it down. The DMA moves data to/from the peripheral transmit/receive
registers. The programmer can use the DMA control registers to configure sources and
destinations of data transfers. Depending on the peripheral, one to four peripheral request sources
are available. This is the most efficient method of data transfer available. Core intervention is not
required after the DMA channel is initialized.
5-4
1.
2.
bset#M_HRIE,x:M_HCR ; enable host receive interrupt
orgP:$60
movepx:M_HRX,x1
movex1,y:(r0)+
Setting up the interrupt routine
a.
b.
Enabling the interrupts
a.
b.
c.
The interrupt handler is located at the interrupt starting address.
The interrupt routines can be short (only two opcodes long) or long (more than two
opcodes and requiring a JSR instruction).
Set the corresponding bits in the applicable peripheral control register.
Enable peripheral interrupts in the Interrupt Priority Register (IPRP).
Enable global interrupts in the Mode Register (MR) portion of the Status Register
(SR).
; HI08 Receive Data Full interrupt
DSP56303 User’s Manual, Rev. 2
Example 5-2. Interrupts
Freescale Semiconductor