SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 109

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

respectively. When host requests are enabled, the host request pins operate as shown in Figure
6-3.
Table 6-5 shows the operation of the
test these ICR bits to determine the interrupt source.
Table 6-6 shows the operation of the transmit request (
with dual host requests enabled.
6.4.5 Endian Modes
The Host Little Endian bit in the host-side Interface Control Register (ICR[5] = HLEND) allows
the host to access the HI08 data registers in Big Endian or Little Endian mode. In Little Endian
mode (HLEND = 1), a host transfer occurs as shown in Figure 6-4.
Freescale Semiconductor
Table 6-6. HTRQ and HRRQ Pin Operation In Double Request Mode (ICR[2] = HDRQ = 1)
ICR[1] = TREQ
Host Request
$2
$0
ICR[1] = TREQ
Table 6-5. HREQ Pin Operation In Single Request Mode (ICR[2] = HDRQ = 0)
Asserted
0
0
1
1
HREQ
7
7
INIT
0
0
1
1
0
0
ICR[0] = RREQ
0
0
0
1
0
1
Figure 6-3. HI08 Host Request Structure
HF3
HF1
ICR[0] = RREQ
HF2 TRDY TXDE RXDF ISR
HF0 HLEND TREQ RREQ ICR
0
1
0
1
DSP56303 User’s Manual, Rev. 2
No interrupts
TXDE Request enabled
TXDE Request enabled
No interrupts
HREQ
pin when a single request line is used. The host can
HTRQ Pin
No interrupts
RXDF request enabled
TXDE request enabled
RXDF and TXDE request enabled
Enable
Status
HTRQ
0
0
) and receive request (
No interrupts
RXDF request enabled
No interrupts
RXDF request enabled
HREQ Pin
HRRQ Pin
Host Request
Signals
HRRQ
HRRQ
HREQ
HTRQ
) lines
Operation
6-9