SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 187

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

and the external clock is used if the SCI is the slave device, as noted above. The clock is gated
and limited to a maximum frequency equal to one eighth of the DSP core operating frequency
(that is, 12.5 MHz for a DSP core frequency of 100 MHz).
For asynchronous operation, the SCI can use the internal and external clocks in any combination
as the source clocks for the TX clock and RX clock. If an external clock is used for the
input, it must be sixteen times the desired bit rate (designated as the 16
Figure 8-6. When the internal clock is used to supply a clock to an external device, the clock can
use the actual bit rate (designated as the 1
COD bit. The output clock is continuous.
When SCKP is cleared, the transmitted data on the
the serial clock and is stable on the positive edge. When SCKP is set, the data changes on the
positive edge and is stable on the negative edge. The received data on the
on the positive edge (if SCKP = 0) or on the negative edge (if SCKP = 1) of the serial clock.
8.6.4 SCI Data Registers
The SCI data registers are divided into two groups: receive and transmit, as shown in Figure 8-7.
There are two receive registers: a Receive Data Register (SRX) and a serial-to-parallel Receive
Shift Register. There are also two transmit registers: a Transmit Data Register (called either STX
or STXA) and a parallel-to-serial Transmit Shift Register.
Freescale Semiconductor
RX, TX Data
(SSFTD = 0)
(SCKP = 0)
x16 Clock
x1 Clock
Idle Line
Start
Figure 8-6. 16 x Serial Clock
DSP56303 User’s Manual, Rev. 2
0
1
×
clock) or the 16
2
3
TXD
4
signal changes on the negative edge of
5
×
Select 8-or 9-bit Words
clock rate, as determined by the
6
7
×
8
clock), as indicated in
RXD
Stop
SCI Programming Model
signal is sampled
Start
SCLK
8-19