SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 211

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.3.4.1 Watchdog Pulse (Mode 9)
In Mode 9, the timer generates an external signal at a preset rate. The signal period is equal to the
period of one timer clock. After the counter reaches the value in the TCPR, if the TCSR[TRM]
bit is set, the counter is loaded with the TLR value on the next timer clock and the count resumes.
Therefore TRM = 1 is not useful for watchdog functions. If the TCSR[TRM] bit is cleared, the
counter continues to increment on each subsequent timer clock. This process repeats until the
timer is disabled (that is, TCSR[TE] is cleared). If the counter overflows, a pulse is output on the
TIO
polarity is high (logical 1). If INV is cleared, the pulse polarity is low (logical 0). The counter
reloads when the TLR is written with a new value while the TCSR[TE] bit is set. In Mode 9,
internal logic preserves the
the hardware
generated when the
Freescale Semiconductor
TC3
1
signal with a pulse width equal to the timer clock period. If the INV bit is set, the pulse
Mode 9 (internal clock): TRM = 0
TIO can connect to the RESET pin, internal hardware preserves the TIO value and
direction for an additional 2.5 clocks to ensure a reset of valid length.
TC2
N = write preload
M = write compare
Bit Settings
TE
Clock
(CLK/2 or prescale CLK)
TLR
TCPR
TCF (Compare Interrupt if TCIE = 1)
0
Counter (TCR)
TOF (Overflow Interrupt if TOIE = 1)
TIO pin (INV = 0)
TIO pin (INV = 1)
RESET
TC1
0
TIO
signal is asserted. This convention ensures that a valid
float
float
signal resets the DSP56303.
TC0
1
TIO
N
M
Figure 9-18. Watchdog Pulse Mode
0
value and direction for an additional 2.5 internal clock cycles after
low
high
Mode
DSP56303 User’s Manual, Rev. 2
9
first event
N
(Software does not reset watchdog timer; watchdog times out)
N + 1
Name
Pulse
Mode Characteristics
M
TRM = 1 is not useful for watchdog function
Watchdog
Function
M + 1
pulse width
clock period
0
RESET
= timer
Output
TIO
1
Operating Modes
signal is
Internal
Clock
9-19