SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 147

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Bit Number
16–12
10–8
7–0
11
Table 7-3. ESSI Control Register A (CRA) Bit Definitions (Continued)
Bit Name
PM[7–0]
DC[4–0]
PSR
Reset Value
0
0
0
0
DSP56303 User’s Manual, Rev. 2
Frame Rate Divider Control
Control the divide ratio for the programmable frame rate dividers that generate
the frame clocks. In Network mode, this ratio is the number of words per frame
minus one. In Normal mode, this ratio determines the word transfer rate. The
divide ratio ranges from 1 to 32 (DC = 00000 to 11111) for Normal mode and 2
to 32 (DC = 00001 to 11111) for Network mode. A divide ratio of one (DC =
00000) in Network mode is a special case known as On-Demand mode. In
Normal mode, a divide ratio of one (DC = 00000) provides continuous periodic
data word transfers. A bit-length frame sync must be used in this case; you
select it by setting the FSL[1–0] bits in the CRA to (01). Figure 7-4 shows the
ESSI frame sync generator functional block diagram.
Prescaler Range
Controls a fixed divide-by-eight prescaler in series with the variable prescaler.
This bit extends the range of the prescaler when a slower bit clock is needed.
When PSR is set, the fixed prescaler is bypassed. When PSR is cleared, the
fixed divide-by-eight prescaler is operational, as in Figure 7-3. This definition
is reversed from that of the SSI in other DSP56000 family members. The
maximum allowed internally generated bit clock frequency is the internal
DSP56303 clock frequency divided by 4; the minimum possible internally
generated bit clock frequency is the DSP56303 internal clock frequency
divided by 4096.
Note:
Reserved. Write to 0 for future compatibility.
Prescale Modulus Select
Specify the divide ratio of the prescale divider in the ESSI clock generator. A
divide ratio from 1 to 256 (PM = $0 to $FF) can be selected. The bit clock
output is available at the transmit clock signal (SCK) and/or the receive clock
(SC0) signal of the DSP. The bit clock output is also available internally for use
as the bit clock to shift the transmit and receive shift registers. Figure 7-3
shows the ESSI clock generator functional block diagram. F
DSP56303 core clock frequency (the same frequency as the enabled
CLKOUT signal). Careful choice of the crystal oscillator frequency and the
prescaler modulus can generate the industry-standard CODEC master clock
frequencies of 2.048 MHz, 1.544 MHz, and 1.536 MHz.
The combination PSR = 1 and PM[7–0] = $00 (dividing F
can cause synchronization problems and thus should not be used.
Description
ESSI Programming Model
core
is the
core
by 2)
7-15