SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 18

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DSP56303 Overview
PCU features include the following:
The PCU uses the following registers:
1.6.4 PLL and Clock Oscillator
The clock generator in the DSP56300 core comprises two main blocks: the PLL, which performs
clock input division, frequency multiplication, and skew elimination; and the clock generator,
which performs low-power division and clock pulse generation. These features allow you to:
The PLL allows the processor to operate at a high internal clock frequency using a low-frequency
clock input, a feature that offers two immediate benefits:
1-8
Position-independent code support
Addressing modes optimized for DSP applications (including immediate offsets)
Instruction cache controller
Internal memory-expandable hardware stack
Nested hardware DO loops
Fast auto-return interrupts
Hardware system stack
Program counter register
Status register
Loop address register
Loop counter register
Vector base address register
Size register
Stack pointer
Operating mode register
Stack counter register
Change the low-power divide factor without losing the lock
Output a clock with skew elimination
A lower-frequency clock input reduces the overall electromagnetic interference generated
by a system.
The ability to oscillate at different frequencies reduces costs by eliminating the need to
add additional oscillators to a system.
DSP56303 User’s Manual, Rev. 2
Freescale Semiconductor