SPAKDSP303AG100 Freescale Semiconductor, SPAKDSP303AG100 Datasheet - Page 140

• Manufacturer Part Number: SPAKDSP303AG100
• Description: IC DSP 24BIT 100MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of SPAKDSP303AG100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 24b
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Synchronous Serial Interface (ESSI)
Note:
To configure an ESSI exception, perform the following steps:
7-8
1.
2.
exception occurs regardless of the transmit mask register setting. The transmit last slot
interrupt can signal that the transmit mask slot register can be reset, the DMA channels
can be reconfigured, and data memory pointers can be reassigned. Using the Transmit Last
Slot interrupt guarantees that the previous frame is serviced with the previous frame
settings and the new frame is serviced with the new frame settings without
synchronization problems.
ESSI transmit data:
Occurs when the transmit interrupt is enabled, at least one of the enabled transmit data
registers is empty, and no transmitter error conditions exist. Write to all the enabled TX
registers or to the TSR to clear this interrupt. This error-free interrupt uses a fast interrupt
service routine for minimum overhead (if no more than two transmitters are used).
Configure the interrupt service routine (ISR):
a.
b.
c.
Configure interrupt trigger; preload transmit data
a.
b.
c.
d.
e.
f.
The example material to the right of the steps shows register settings for configuring an
ESSI0 transmit interrupt using transmitter 0. The order of the steps is optional except
that the interrupt trigger configuration must not be completed until the ISR
configuration is complete. Since step 2c may cause an immediate transmit without
generating an interrupt, perform the transmit data preload in step 2b before step 2c to
ensure that valid data is sent in the first transmission.
The maximum transmit last slot interrupt service time should not exceed
N – 1 ESSI bits service time (where N is the number of bits in a slot).
Load vector base address register
Define I_VEC to be equal to the VBA value (if that is nonzero). If it is defined,
I_VEC must be defined for the assembler before the interrupt equate file is
included.
Load the exception vector table entry: two-word fast interrupt, or jump/branch to
subroutine (long interrupt).
Enable and prioritize overall peripheral interrupt functionality.
Write data to all enabled transmit registers.
Enable a peripheral interrupt-generating function.
Enable a specific peripheral interrupt.
Enable peripheral and associated signals.
Unmask interrupts at the global level.
DSP56303 User’s Manual, Rev. 2
VBA (b23:8)
p:I_SI0TD
IPRP (S0L1:0)
TX00
CRB0 (TIE)
PCRC (PC[5–0])
SR (I1–0)
CRB (TE0)
Freescale Semiconductor